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公开(公告)号：US10998020B1
公开(公告)日：2021-05-04
申请号：US16866886
申请日：2020-05-05
发明人： Fu-Chin Tsai , Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou , Kuo-Wei Chi , Shih-Chang Chen , Shih-Han Lin , Min-Han Tsai
摘要： The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.
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公开(公告)号：US12088359B2
公开(公告)日：2024-09-10
申请号：US17938050
申请日：2022-10-05
发明人： Shih-Chang Chen , Chih-Wei Chang , Chun-Chi Yu
IPC分类号： H04B17/345
CPC分类号： H04B17/345
摘要： An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.
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公开(公告)号：US11848802B2
公开(公告)日：2023-12-19
申请号：US17677177
申请日：2022-02-22
发明人： Peng-Fei Lin , Chen-Yuan Chang , Shih-Chang Chen
CPC分类号： H04L25/03044 , H04L25/03229 , H04L25/10 , H04L2025/0377 , H04L2025/03815
摘要： The present invention discloses a receive data equalization apparatus. A delay-compensating calculation circuit retrieves training data groups of a training data signal to retrieve total delay amount, generate signed compensation amounts according to a relation among training data contents of training data in each of the training data groups to generate total compensation amount accordingly, and solve equations that correspond total delay amount of the training data groups to the total compensation amount to obtain each of the compensation amounts. A receive data equalization circuit receives the compensation amounts and retrieves a receive data group in a receive data signal, generate signed receive compensation amounts according to a relation among receive data contents of receive data in the receive data group to generate a total receive compensation amount accordingly to perform equalization on a terminal edge of the receive data group according to the total receive compensation amount.
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公开(公告)号：US09570130B2
公开(公告)日：2017-02-14
申请号：US15093758
申请日：2016-04-08
发明人： Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou , Fu-Chin Tsai , Shih-Chang Chen
IPC分类号： G11C7/22
摘要： A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a dock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information therein transmitted by the memory controller according to a write-related clock signal and retrieves the input information therefrom according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the memory device to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.
摘要翻译： 提供电连接在存储器控制器和存储器件之间的存储器物理层接口电路。 存储器物理层接口电路包括坞站生成模块和先进先出（FIFO）模块。 时钟产生模块产生参考时钟信号并输出相关的时钟信号。 参考时钟信号被发送到存储器件。 每个FIFO模块根据写相关的时钟信号将存储器控制器发送的输入信息写入其中，并根据输出相关时钟信号之一检索输入信息，以产生输出信号。 输出信号被传送到存储器件以操作存储器件。 写相关时钟信号是通过除去输出相关时钟信号之一的频率而产生的。
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公开(公告)号：US10698846B2
公开(公告)日：2020-06-30
申请号：US16182680
申请日：2018-11-07
发明人： Kuo-Wei Chi , Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou , Shih-Chang Chen
摘要： Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.
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