公开(公告)号：US20180224883A1

公开(公告)日：2018-08-09

申请号：US15423829

申请日：2017-02-03

Applicant: Raytheon Company

Inventor： Terence J. McKiernan ,  Ray B. Huffaker ,  Daniel G. Miller ,  David A. Blaser ,  Ryan D. Retting ,  Harry B. Marr

IPC: G06F1/12 ,  G06F17/50 ,  G06F9/54

CPC classification number: G06F9/546 ,  G06F1/10 ,  G06F9/52 ,  G06F17/5022 ,  G06F2217/62

Abstract: A system includes a first simulated processing system having a first clock and a second simulated processing system having a second clock. The first and second processing systems may operate asynchronously. A synchronization bridge may coordinate executing of the first synchronized processing system and the second synchronized processing system to synchronize the time of execution of the first and second simulated processing systems and messaging between the first and second processing systems. The first and second processing systems may be simulated processing systems.

公开(公告)号：US10409321B2

公开(公告)日：2019-09-10

申请号：US15423829

申请日：2017-02-03

Applicant: Raytheon Company

Inventor： Terence J. McKiernan ,  Ray B. Huffaker ,  Daniel G. Miller ,  David A. Blaser ,  Ryan D. Retting ,  Harry B. Marr

IPC: G06F1/12 ,  G06F9/54 ,  G06F17/50

Abstract: A system includes a first simulated processing system having a first clock and a second simulated processing system having a second clock. The first and second processing systems may operate asynchronously. A synchronization bridge may coordinate executing of the first synchronized processing system and the second synchronized processing system to synchronize the time of execution of the first and second simulated processing systems and messaging between the first and second processing systems. The first and second processing systems may be simulated processing systems.