公开(公告)号：US12093533B1

公开(公告)日：2024-09-17

申请号：US18218257

申请日：2023-07-05

申请人： Radian Memory Systems, LLC

发明人： Andrey V. Kuzmin ,  Alan Chen ,  Robert Lercari

IPC分类号： G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0616 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7211

摘要： This disclosure provides techniques for managing memory which match per-data metrics to those of other data or to memory destination. In one embodiment, wear data is tracked for at least one tier of nonvolatile memory (e.g., flash memory) and a measure of data persistence (e.g., age, write frequency, etc.) is generated or tracked for each data item. Memory wear management based on these individually-generated or tracked metrics is enhanced by storing or migrating data in a manner where persistent data is stored in relatively worn memory locations (e.g., relatively more-worn flash memory) while temporary data is stored in memory that is less worn or is less susceptible to wear. Other data placement or migration techniques are also disclosed.

公开(公告)号：US09542118B1

公开(公告)日：2017-01-10

申请号：US14880529

申请日：2015-10-12

申请人： Radian Memory Systems, LLC

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F3/06 ,  G06F12/10

CPC分类号： G06F12/1009 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0662 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

摘要： This disclosure provides techniques of hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

摘要翻译： 本公开提供了存储器控制器内的分层地址虚拟化和可配置块设备分配的技术。 通过仅在选择的层次级别执行地址转换，可以将存储器控制器设计为具有可预测的I / O延迟，具有简短或其他可忽略的逻辑到物理地址转换时间。 在一个实施例中，地址转换可以完全用存储器控制器集成电路的逻辑门和查找表来实现，而不需要处理器周期。 所公开的虚拟化方案还提供了定制虚拟存储设备的配置的灵活性，以向主机或客户端呈现几乎任何期望的配置。

公开(公告)号：US09588904B1

公开(公告)日：2017-03-07

申请号：US15053372

申请日：2016-02-25

申请人： Radian Memory Systems, LLC

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/10 ,  G06F12/02 ,  G06F3/06

CPC分类号： G06F12/1009 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0662 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

摘要： Hierarchical address virtualization within a memory controller and configurable block device allocation are disclosed. Respective virtual block devices (VBDs) are defined in flash memory managed by a common memory controller, with data access managed using address virtualization techniques. The common memory controller then tracks the need for maintenance operations independently for each VBD. Information may be received from the common memory controller regarding the need for maintenance operations in respective virtual block devices (VBDs), and commands are then selectively issued to the common memory controller in a manner so as to independently schedule these operations for the respective VBDs; performance of maintenance operations by the memory controller in a first VBD is unconstrained by performance characteristics associated with a second VBD.

摘要翻译： 公开了内存控制器内的分层地址虚拟化和可配置的块设备分配。 各个虚拟块设备（VBD）在由公共存储器控制器管理的闪存中定义，使用地址虚拟化技术管理数据访问。 然后，公共存储器控制器针对每个VBD独立地跟踪维护操作的需要。 可以从公共存储器控制器接收关于在各个虚拟块设备（VBD）中的维护操作的需要的信息，然后以各种VBD独立地调度这些操作的方式选择性地向公共存储器控制器发出命令; 通过第一VBD中的存储器控​​制器的维护操作的性能不受与第二VBD相关联的性能特性的约束。

公开(公告)号：US09785572B1

公开(公告)日：2017-10-10

申请号：US15074778

申请日：2016-03-18

申请人： Radian Memory Systems, LLC

发明人： Robert Lercari ,  Alan Chen ,  Mike Jadon ,  Craig Robertson ,  Andrey V. Kuzmin

IPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F12/109

CPC分类号： G06F12/1009 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0662 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/109 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

摘要： This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.