公开(公告)号：US09270443B2

公开(公告)日：2016-02-23

申请号：US14609924

申请日：2015-01-30

申请人： ROHM CO., LTD.

发明人： Shinichi Saito

IPC分类号： H04L27/00 ,  H04L7/00 ,  H04L7/04

CPC分类号： H04L7/0054 ,  H04L7/043

摘要： Transmission circuit for transmitting serial data with superposed clock signal includes encoder to scramble parallel data of information and apply predetermined coding scheme to generate D symbols having clock signal embedded therein, and to output alternately continuous predetermined number of the D symbols and one of K symbols as synchronization control codes for the scrambling; and parallel-to-serial converter configured to convert the D symbols and the K symbols output from the encoder into serial data, wherein, for each period of the scrambling, the encoder outputs K symbols, each of which is allocated to one of the first code indicating beginning of the period of the scrambling, the second code allocated at equal interval among remaining ones of the K symbols other than that for the first code, and a third code allocated among remaining ones of the K symbols other than those for the first code and the second code.

公开(公告)号：US09503253B2

公开(公告)日：2016-11-22

申请号：US14994659

申请日：2016-01-13

申请人： ROHM CO., LTD.

发明人： Shinichi Saito

IPC分类号： H04L27/00 ,  H04L7/00 ,  H04L7/04

CPC分类号： H04L7/0054 ,  H04L7/043

摘要： Transmission circuit for transmitting serial data with superposed clock signal includes encoder to scramble parallel data of information and apply predetermined coding scheme to generate D symbols having clock signal embedded therein, and to output alternately continuous predetermined number of the D symbols and one of K symbols as synchronization control codes for the scrambling; and parallel-to-serial converter configured to convert the D symbols and the K symbols output from the encoder into serial data, wherein, for each period of the scrambling, the encoder outputs K symbols, each of which is allocated to one of the first code indicating beginning of the period of the scrambling, the second code allocated at equal interval among remaining ones of the K symbols other than that for the first code, and a third code allocated among remaining ones of the K symbols other than those for the first code and the second code.

摘要翻译： 用于发送具有叠加时钟信号的串行数据的发送电路包括编码器，用于对信息的并行数据进行加扰，并施加预定的编码方案以产生嵌入时钟信号的D个符号，并交替输出连续的预定数量的D个符号和K个符号中的一个作为 用于加扰的同步控制码; 以及并行转换器，被配置为将从编码器输出的D个符号和K个符号转换为串行数据，其中，对于加扰的每个周期，编码器输出K个符号，每个符号分配给第一个 指示加扰周期的开始的代码，除了第一代码之外的K个符号中的其余的K个符号中以相等的间隔分配的第二代码以及除了第一代码之外的K个符号的其余的K个符号中分配的第三代码 代码和第二个代码。

公开(公告)号：US09209807B2

公开(公告)日：2015-12-08

申请号：US14312828

申请日：2014-06-24

申请人： ROHM CO., LTD.

发明人： Shinichi Saito

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： H03K19/00361 ,  H03K19/0016

摘要： A differential receiver for receiving differential signals including a positive signal and a negative signal and generating an output signal is provided. The differential receiver includes a first comparator configured to compare the positive signal and the negative signal and generate a first signal that is asserted when a difference between the positive signal and the negative signal is larger than a positive offset voltage; a second comparator configured to compare the positive signal and the negative signal and generate a second signal that is asserted when the difference between the positive signal and the negative signal is smaller than a negative offset voltage; a logic gate configured to generate a third signal that is asserted when the first signal and the second signal are negated; and an output circuit configured to generate the output signal based on the first to third signals.

摘要翻译： 提供了用于接收包括正信号和负信号并产生输出信号的差分信号的差分接收器。 差分接收器包括：第一比较器，被配置为比较正信号和负信号，并产生当正信号和负信号之间的差大于正偏移电压时被断言的第一信号; 第二比较器，被配置为比较正信号和负信号，并产生当正信号和负信号之间的差小于负偏移电压时被断言的第二信号; 逻辑门，被配置为产生当所述第一信号和所述第二信号被否定时被断言的第三信号; 以及输出电路，被配置为基于第一至第三信号产生输出信号。

公开(公告)号：US10050611B2

公开(公告)日：2018-08-14

申请号：US15146242

申请日：2016-05-04

申请人： ROHM CO., LTD.

发明人： Shinichi Saito

IPC分类号： H03B27/00 ,  H03K5/15 ,  H03L7/08 ,  H04L7/00 ,  G06F1/06 ,  H03K3/03 ,  H03L7/087

摘要： An oscillation circuit includes: an oscillator configured to generate N phase clocks (where N is an integer of 2 or more) including a first phase clock to Nth phase clock whose phases are shifted by 360°/N at regular intervals; a pulse generating part configured to receive a plurality of the N phase clocks and generate a plurality of intermediate pulses each having a duty ratio of 25%; and a clock synthesizing part configured to synthesize the plurality of intermediate pulses to generate a single phase output clock or multi-phase output clocks, the single phase output clock and the multi-phase output clocks having a frequency that is twice an oscillation frequency of the oscillator.

公开(公告)号：US09461774B2

公开(公告)日：2016-10-04

申请号：US14609903

申请日：2015-01-30

申请人： ROHM CO., LTD.

发明人： Shinichi Saito

IPC分类号： H04L1/00 ,  G06F11/00 ,  H04N19/89 ,  H04N19/436

CPC分类号： H04L1/0061 ,  H04N19/436 ,  H04N19/89

摘要： A reception circuit for receiving serial data including first pixel data constituting image data from a transmission circuit, wherein the serial data has a format allowing the reception circuit to detect a transmission error, the reception circuit including a serial-to-parallel converter configured to receive the serial data and convert the received serial data into first parallel data, an error detector configured to determine whether the first parallel data is correct or erroneous based on the first parallel data, a correcting buffer configured to maintain the first pixel data included in the first parallel data if the first parallel data is determined to be correct by the error detector, and a correcting unit configured to substitute the first pixel data included in the first parallel data determined to be erroneous by the error detector with a value corresponding to second pixel data stored in the correcting buffer.

摘要翻译： 一种用于从发送电路接收包括构成图像数据的第一像素数据的串行数据的接收电路，其中串行数据具有允许接收电路检测传输错误的格式，该接收电路包括被配置为接收的串行到并行转换器 串行数据并将接收到的串行数据转换为第一并行数据;错误检测器，被配置为基于第一并行数据确定第一并行数据是正确还是错误;校正缓冲器，被配置为保持包括在第一并行数据中的第一像素数据; 并行数据，如果第一并行数据被错误检测器确定为是正确的，以及校正单元，被配置为将由误差检测器确定为错误的第一并行数据中包括的第一像素数据替换为与第二像素数据相对应的值 存储在校正缓冲器中。