公开(公告)号：US10903847B2

公开(公告)日：2021-01-26

申请号：US16717070

申请日：2019-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuo Matsui ,  Keisaku Sento ,  Tomohiko Ebata

IPC: H03M1/12 ,  H03M1/46

Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed. According to one embodiment, the analog-to-digital conversion circuit includes a first digital-to-analog conversion circuit 30 of a capacitance distribution type, a second digital-to-analog conversion circuit 31 of a capacitance distribution type, and a comparison circuit 32 for comparing output voltages of the two digital-to-analog conversion circuits, and before performing a successive comparison operation for successively changing a reference voltage applied to the first digital-to-analog conversion circuit, generates an intermediate digital value having a digital value corresponding to a voltage value of an analog input signal, determines a reference voltage to be applied to the second digital-to-analog conversion circuit 31 in accordance with the intermediate digital value, and thereafter performs a successive comparison operation using the first digital-to-analog conversion circuit 30 in a state in which the state of the second digital-to-analog conversion circuit 31 is held.

公开(公告)号：US08994569B2

公开(公告)日：2015-03-31

申请号：US14023642

申请日：2013-09-11

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko Ebata ,  Takuji Aso

IPC: H03M1/12 ,  H03M1/10

CPC classification number: H03M1/1076 ,  H03M1/12 ,  H03M1/1225

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.

Abstract translation: 半导体集成电路器件包括在模拟/数字转换电路的输入端口A [k]和输入端子Ain之间的T型开关电路TS [k]，并且包括第一，第二和第三PMOS晶体管MP1 ，MP2和MPc以及第一，第二和第三NMOS晶体管MN1，MN2和MNc; 以及用于将输入端子Ain预充电到电源电压VCCA的第四PMOS晶体管MPu。 在检测到从输入端口A [k]到信号输入端子Vint [k]的断开的存在或不存在时，首先，输入端子Ain经由第四PMOS晶体管MPu预充电到电源电压VCCA， 第二NMOS晶体管MN2和第二PMOS晶体管MP2也被导通，并且第一NMOS晶体管MN1，第一PMOS晶体管MP1，第三PMOS晶体管MPc和第三NMOS晶体管MNc截止。

公开(公告)号：US11677412B2

公开(公告)日：2023-06-13

申请号：US17529885

申请日：2021-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko Ebata

IPC: H03M1/66 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/46 ,  H03M1/1245

Abstract: A semiconductor device performs sequential comparison of an analog input signal and a reference voltage to digitally convert the analog input signal. The semiconductor device includes an upper DAC generating a high-voltage region of the reference voltage based on a predetermined code, a lower DAC generating a low-voltage region of the reference voltage based on the code, and an injection DAC having the same configuration as that of the lower DAC and adjusting the low-voltage region of the reference voltage.

公开(公告)号：US09438260B1

公开(公告)日：2016-09-06

申请号：US15012889

申请日：2016-02-02

Applicant: Renesas Electronics Corporation

Inventor： Tomohiko Ebata

IPC: H03M1/00 ,  H03M1/10

CPC classification number: H03M1/1038 ,  H03M1/164

Abstract: In a conventional calibration method of an analog to digital converter, it has been difficult to easily derive a plurality of correction coefficients. A semiconductor apparatus according to an embodiment includes a plurality of unit elements that are provided to correspond to the total number of weights for each bit of the digital intermediate value b[1:0] output from a sub ADC, and the same capacitance, the same resistance value, or the same current value being set to the plurality of unit elements. Further included is a corresponding bit switching unit configured to switches the bits of the digital intermediate value based on which the plurality of unit elements generate analog values. At the time of calibration, combinations of the plurality of unit elements and the bits are rotated, and correction coefficients are derived by digital intermediate values obtained according to each combination.

Abstract translation: 在模数转换器的常规校准方法中，难以容易地导出多个校正系数。 根据实施例的半导体装置包括多个单元元件，其被提供以对应于从副ADC输出的数字中间值b [1：0]的每个位的总重量，以及相同的电容， 相同的电阻值或相同的电流值被设置到多个单位元件。 另外包括对应的比特切换单元，被配置为切换数字中间值的比特，基于该比特，多个单元生成模拟值。 在校准时，旋转多个单位元件和位的组合，并且通过根据每个组合获得的数字中间值导出校正系数。

公开(公告)号：US09300313B2

公开(公告)日：2016-03-29

申请号：US14666406

申请日：2015-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiko Ebata ,  Takuji Aso

IPC: H03M1/12 ,  H03M1/10

CPC classification number: H03M1/1076 ,  H03M1/12 ,  H03M1/1225

Abstract: The semiconductor integrated circuit device includes a T-type switch circuit TS[k] that is between an input port A[k] and an input terminal Ain of an analog/digital conversion circuit and that includes first, second, and third PMOS transistors MP1, MP2, and MPc, and first, second, and third NMOS transistors MN1, MN2, and MNc; and a fourth PMOS transistor MPu for pre-charging the input terminal Ain to a power supply voltage VCCA. In detecting the presence or absence of a disconnection from the input port A[k] to a signal input terminal Vint[k], first, the input terminal Ain is pre-charged to the power supply voltage VCCA via the fourth PMOS transistor MPu and also the second NMOS transistor MN2 and the second PMOS transistor MP2 are turned on, and the first NMOS transistor MN1, the first PMOS transistor MP1, the third PMOS transistor MPc, and third the NMOS transistor MNc are turned off.