公开(公告)号：US12034469B2

公开(公告)日：2024-07-09

申请号：US17127709

申请日：2020-12-18

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Umesh Srikantiah ,  Karthik Manivannan

IPC: H04W48/18 ,  G06F13/40 ,  G06F13/42 ,  H04B1/401 ,  H04W88/06

CPC classification number: H04B1/401 ,  G06F13/4027 ,  G06F13/4291

Abstract: Systems and methods for variable stride counting for timed-triggers in a radio frequency front end (RFFE) bus modify how a master clock controls counters in slaves. In particular, instead of having the master clock change a counter at a slave device on a one-to-one clock tick-to-counter change, exemplary aspects of the present disclosure contemplate allowing a bus ownership master (BOM) to select a stride size wherein each clock tick causes the counter to change by the size of the stride. Clock ticks are then sent less frequently over the clock line of the RFFE bus. In this fashion, fewer clock ticks are required to change the counter to the trigger event.

公开(公告)号：US11556486B2

公开(公告)日：2023-01-17

申请号：US16920150

申请日：2020-07-02

Applicant: QUALCOMM Incorporated

Inventor： Mohit Kishore Prasad ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/362 ,  G06F13/42

Abstract: An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.

公开(公告)号：US11531608B2

公开(公告)日：2022-12-20

申请号：US17027541

申请日：2020-09-21

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Lalan Jee Mishra

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/07 ,  G06F11/10 ,  G06F13/42

Abstract: Systems, methods, and apparatus for error signaling on a serial bus are described. An apparatus includes a bus interface configured to couple the apparatus to a serial bus, a phase-differential decoder configured to decode data from transitions between pairs of symbols in a sequence of symbols received from the serial bus, each symbol being representative of signaling state of the serial bus, and a processor configured to detect an indicator of an error signaling window in signaling state of two wires of the serial bus, the indicator of the error signaling window corresponding to a prohibited combination of symbols or a delay in control signaling, signaling an error through the bus interface during the error signaling window when an error is detected in the sequence of symbols or in timing of the indicator of the error signaling window.

公开(公告)号：US11520729B2

公开(公告)日：2022-12-06

申请号：US17307842

申请日：2021-05-04

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Sharon Graif ,  Lior Amarilio ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F1/08 ,  G06F13/20

Abstract: Systems, methods, apparatus and techniques are described that provide point-to-point capabilities without the expected increase in input/output pad usage. In some examples, point-to-point data lines are provided between a host and multiple slave devices and timing of communication is controlled using a clock signal shared by the multiple slave devices. An apparatus has a plurality of bus master circuits configured to control point-to-point communication with corresponding slave devices and a clock generation circuit configured to provide pulses in a serial bus clock signal when one or more bus master circuits are in an active state, and further to idle the serial bus clock signal when all bus master circuits are idle. Each bus master circuit may be configured to communicate with its corresponding slave device in accordance with the timing provided by the serial bus clock signal that is transmitted over a common clock line to each slave device.

公开(公告)号：US11275703B1

公开(公告)日：2022-03-15

申请号：US17024258

申请日：2020-09-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  Irfan Khan

IPC: G06F13/20 ,  G06F13/42

Abstract: Systems, methods, and apparatus for multi-drop coexistence management are described. A data communication apparatus has a bus interface that couples the data communication apparatus to a serial bus and a controller configured to determine that a datagram received from the serial bus is addressed to a register address corresponding to a coexistence management identifier, activate a line driver of the bus interface circuit that is coupled to a data line of the serial bus during a portion of a first payload of the datagram when one or more coexistence management messages are ready for sending from the slave device, where the portion of the first payload of the datagram is allocated for use of the apparatus, and transmit a first coexistence management message in the portion of the first payload of the datagram that is allocated for use of the data communication apparatus.

公开(公告)号：US11119966B2

公开(公告)日：2021-09-14

申请号：US16546495

申请日：2019-08-21

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/362 ,  G06F13/38 ,  G06F13/42

Abstract: The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

公开(公告)号：US11106620B1

公开(公告)日：2021-08-31

申请号：US16841865

申请日：2020-04-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F1/04

Abstract: Systems, methods, and apparatus for improving addressability of slave devices coupled to a serial bus are described. A method the slave device includes delaying transitions in a control signal received at an input pin of the slave device, enabling a counter after detecting a delayed first transition in the control signal, where the counter is configured to count pulses on a data line of a serial bus, transmitting a first pulse on the data line of the serial bus after enabling the counter, counting the first pulse and one or more additional pulses on the data line of the serial bus, and using an output of the counter to generate a unique identifier used for communicating over the serial bus. Each of a plurality of slave devices may be configured to transmit one of the additional pulses on the serial bus after the first transition occurs in the control signal.

公开(公告)号：US10997114B2

公开(公告)日：2021-05-04

申请号：US16393081

申请日：2019-04-24

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Helena Deirdre O'Shea

IPC: G06F13/42 ,  G06F1/12 ,  G06F13/364

Abstract: Systems, methods, and apparatus for improving throughput of a serial bus are described. A method performed at a device coupled to a serial bus includes detecting a transition in signaling state of a first wire of the serial bus while a first pair of consecutive bits is being received from the first wire of the serial bus, determining that no transition in signaling state of the first wire occurred while a second pair of consecutive bits is being received from the first wire, defining bit values for the first pair of consecutive bits based on direction of the transition in signaling state detected while the first pair of consecutive bits is being received, and sampling the signaling state of the first wire while the second pair of consecutive bits is being received to obtain a bit value used to represent both bits in the second pair of consecutive bits.

公开(公告)号：US10684981B2

公开(公告)日：2020-06-16

申请号：US16381189

申请日：2019-04-11

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Sharon Graif ,  Richard Dominic Wietfeldt

IPC: G06F13/42

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

公开(公告)号：US10417172B2

公开(公告)日：2019-09-17

申请号：US15685783

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Douglas Wayne Hoffman

IPC: G06F13/42

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A method includes transmitting a first command on a serial bus while operating in a first mode of operation, exchanging first data with the first device in accordance with a second protocol associated with the second mode of operation, and exchanging second data with the first device in accordance with the second protocol after the first period of time. The first command may be transmitted in accordance with a first protocol to cause a first device to operate in a second mode of operation. The first device may be idle for a first period of time after the first data has been exchanged.