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    Techniques for timed-trigger and interrupt coexistence
    1.
    发明授权
    Techniques for timed-trigger and interrupt coexistence 有权

    公开(公告)号：US11088815B1

    公开(公告)日：2021-08-10

    申请号：US17062118

    申请日：2020-10-02

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Umesh Srikantiah ,  Karthik Manivannan

    IPC: H04L7/00 ,  H04B7/212 ,  H04W24/10

    Abstract: Certain aspects of the present disclosure provide an apparatus for wireless communication. The apparatus generally includes a plurality of slave radio frequency (RF) devices, a master RF device configured to set a configuration parameter in a register to be applied by an RF slave device of the plurality of RF slave devices, and a clock line coupled between the master RF device and the plurality of slave RF devices. The slave RF device may be configured to: count a number of cycles of a clock signal on the clock line; and apply the configuration parameter for the slave RF device based on the count of the number of cycles, wherein the master RF device is further configured to disable an interrupt reporting function of the plurality of slave RF device during a time period between setting the configuration parameter in the register and the configuration parameter being applied.

    Independent addressing of one-wire and two-wire devices on a shared RFFE bus interface
    2.
    发明授权
    Independent addressing of one-wire and two-wire devices on a shared RFFE bus interface 有权

    公开(公告)号：US12124400B2

    公开(公告)日：2024-10-22

    申请号：US18157000

    申请日：2023-01-19

    Applicant: QUALCOMM Incorporated

    Inventor： Umesh Srikantiah ,  Lalan Jee Mishra ,  Francesco Gatta ,  Richard Dominic Wietfeldt

    IPC: G06F13/00 ,  G06F13/42

    CPC classification number: G06F13/4291

    Abstract: A data communication apparatus coupled to a serial bus has a protocol controller that configures a first plurality of subordinate devices with device identifiers unique within the first plurality of subordinate devices and configures a second plurality of subordinate devices with device identifiers unique within the second plurality of subordinate devices. A sequence start condition transmitted over the serial bus indicates either a first communication mode in which a clock signal is provided to the serial bus or a second communication mode in which no clock signal is provided. A device identifier associated with the first plurality of subordinate devices is used to transmit a first datagram over the serial bus in the first communication mode, and a device identifier associated with the second plurality of subordinate devices is used to transmit a second datagram over the serial bus in the second communication mode.

    One-wire bidirectional bus signaling with manchester encoding
    3.
    发明授权
    One-wire bidirectional bus signaling with manchester encoding 有权

    公开(公告)号：US11886366B2

    公开(公告)日：2024-01-30

    申请号：US17677731

    申请日：2022-02-22

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

    IPC: G06F13/362 ,  G06F1/12 ,  G06F13/42 ,  H04L12/40

    CPC classification number: G06F13/362 ,  G06F1/12 ,  G06F13/4282 ,  H04L12/40

    Abstract: An apparatus coupled to a single-wire serial bus through a line driver is configured to determine that a first sequence start condition (SSC) has been initiated when the single-wire serial bus transitions from first to second signaling states. The line driver drives the single-wire serial bus to the first signaling state after a first duration to complete the first SSC, and an arbitration window with plural timeslots is provided when the line driver presents a high impedance to the single-wire serial bus after the first SSC. The line driver drives the single-wire serial bus to the first signaling state in each timeslot of the plural timeslots in which the single-wire serial bus is driven to the second signaling state. After the arbitration window has expired, the apparatus transmits a second SSC and a Manchester encoded command addressed to at least one slave device.

    Controlling the application time of radio frequency front end triggers based on execution of sequences
    7.
    发明授权
    Controlling the application time of radio frequency front end triggers based on execution of sequences 有权

    公开(公告)号：US11327912B2

    公开(公告)日：2022-05-10

    申请号：US17003697

    申请日：2020-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Reza Rodd ,  Scott Davenport ,  Umesh Srikantiah ,  ZhenQi Chen

    IPC: G06F3/00 ,  G06F13/20 ,  G06F13/42 ,  H04L69/323 ,  H04B1/40

    Abstract: Systems, methods, and apparatus for improving bus latency are described. A data communication method includes receiving a trigger actuation command from a bus master coupled to the serial bus, determining that a sequence is being executed in the slave device, and providing a trigger actuation signal corresponding to the trigger actuation command when execution of the sequence has been completed. A sequence initiation command may be received before the trigger actuation command, and the sequence may be initiated in response to the sequence initiation command. The trigger actuation command may be queued in a first queue, the sequence initiation command in may be queued in a second queue. Trigger actuation commands in the first queue may be associated with sequence initiation commands in the second queue. The sequence may be initiated in response to a sequence initiation command associated with the trigger actuation command corresponding to the trigger actuation signal.

    Intra-module serial communication interface for radio frequency devices
    8.
    发明授权
    Intra-module serial communication interface for radio frequency devices 有权

    公开(公告)号：US11243902B2

    公开(公告)日：2022-02-08

    申请号：US17003724

    申请日：2020-08-26

    Applicant: QUALCOMM Incorporated

    Inventor： Reza Rodd ,  Scott Davenport ,  Umesh Srikantiah ,  ZhenQi Chen

    IPC: G06F13/40 ,  G06F13/42 ,  H04B1/40

    Abstract: Systems, methods, and apparatus for improving bus latency and reducing bus congestion are described. A data communication apparatus has a first interface circuit configured to couple the data communication apparatus to a primary serial bus, a second interface circuit configured to couple the data communication apparatus to a plurality of secondary serial buses, and a sequencer configured to respond to a first command received from the primary serial bus by initiating execution of a preconfigured sequence that causes a sequence of commands to be transmitted through the second interface circuit. The sequence of commands may be configured or selected to access registers in at least one device that is coupled to one of the secondary serial buses.

    Automatic clock rate synchronization for 1-wire radio frequency front-end interface
    9.
    发明授权
    Automatic clock rate synchronization for 1-wire radio frequency front-end interface 有权

    公开(公告)号：US12283961B2

    公开(公告)日：2025-04-22

    申请号：US18449554

    申请日：2023-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

    IPC: H03K5/24 ,  H03K3/037 ,  H03K3/356

    Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

    Error handling for a mixed mode RFFE bus
    10.
    发明授权
    Error handling for a mixed mode RFFE bus 有权

    公开(公告)号：US12248365B2

    公开(公告)日：2025-03-11

    申请号：US18183833

    申请日：2023-03-14

    Applicant: QUALCOMM Incorporated

    Inventor： Umesh Srikantiah ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Boris Alpin ,  Francesco Gatta

    IPC: G06F11/07 ,  G06F13/42

    Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

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