公开(公告)号：US20230325576A1

公开(公告)日：2023-10-12

申请号：US17655823

申请日：2022-03-22

Applicant: QUALCOMM Incorporated

Inventor： Siddharth Kamdar ,  Christophe Avoinne ,  Sanjay Jaisingh Arya ,  Manav Shah

IPC: G06F30/394 ,  G11C5/06 ,  G11C8/12

CPC classification number: G06F30/394 ,  G11C5/06 ,  G11C8/12

Abstract: Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

公开(公告)号：US11972189B2

公开(公告)日：2024-04-30

申请号：US17655823

申请日：2022-03-22

Applicant: QUALCOMM Incorporated

Inventor： Siddharth Kamdar ,  Christophe Avoinne ,  Sanjay Jaisingh Arya ,  Manav Shah

IPC: G11C5/06 ,  G06F30/394 ,  G11C8/12

CPC classification number: G06F30/394 ,  G11C5/06 ,  G11C8/12

Abstract: Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

公开(公告)号：US10769073B2

公开(公告)日：2020-09-08

申请号：US15939031

申请日：2018-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： Kunal Desai ,  Satyaki Mukherjee ,  Siddharth Kamdar ,  Abhinav Mittal ,  Vinayak Shrivastava

IPC: G06F12/10 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for managing memory channel connectivity. One embodiment of a system comprises a high-bandwidth memory client, a low-bandwidth memory client, and an address translator. The high-bandwidth memory client is electrically coupled to each of a plurality of memory channels via an interconnect. The low-bandwidth memory client is electrically coupled to only a portion of the plurality of memory channels via the interconnect. The address translator is in communication with the high-bandwidth memory client and configured to perform physical address manipulation when a memory page to be accessed by the high-bandwidth memory client is shared with the low-bandwidth memory client.