公开(公告)号：US20180150394A1

公开(公告)日：2018-05-31

申请号：US15647202

申请日：2017-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ramasamy ADAIKKALAVAN ,  Harish SHANKAR ,  Rajesh KUMAR

IPC: G06F12/0808 ,  G06F17/30 ,  G06F12/1045 ,  G06F12/1009

CPC classification number: G06F12/0808 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1045 ,  G06F16/90339 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G11C15/04

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

公开(公告)号：US20170047918A1

公开(公告)日：2017-02-16

申请号：US14860713

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Manish GARG ,  Ramasamy ADAIKKALAVAN

IPC: H03K5/24 ,  G06F12/08 ,  H03K19/20

CPC classification number: H03K5/24 ,  G06F7/026 ,  G06F12/0802 ,  G06F2212/60 ,  H03K19/20

Abstract: Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.

Abstract translation: 公开的系统和方法涉及第一个数字和第二个数字的比较。 比较器接收可以是n位宽的第一和第二单端输入（即，不以差分格式表示），其中第一输入是第一数字的反转版本，第二输入是真实版本的 第二个数字。 实现部分匹配电路以仅基于第一单端输入和第二单端输入来产生部分匹配输出。 实现部分失配电路以仅基于第一单端输入和第二单端输入产生部分失配输出。 实现比较输出电路，以基于部分匹配输出和部分失配输出来产生第一和第二数字的比较输出。