公开(公告)号：US20190214076A1

公开(公告)日：2019-07-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish SHANKAR ,  Manish GARG ,  Rahul Krishnakumar NADKARNI ,  Rajesh KUMAR ,  Michael PHAN

IPC: G11C11/419

Abstract: Disclosed is a memory system comprising a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：US20180150394A1

公开(公告)日：2018-05-31

申请号：US15647202

申请日：2017-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ramasamy ADAIKKALAVAN ,  Harish SHANKAR ,  Rajesh KUMAR

IPC: G06F12/0808 ,  G06F17/30 ,  G06F12/1045 ,  G06F12/1009

CPC classification number: G06F12/0808 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1045 ,  G06F16/90339 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2212/68 ,  G11C15/04

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

公开(公告)号：US20180088829A1

公开(公告)日：2018-03-29

申请号：US15710108

申请日：2017-09-20

Applicant: QUALCOMM Incorporated

Inventor： Harish SHANKAR ,  Manish GARG

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/401 ,  G06F2212/6032 ,  G11C15/00 ,  G11C15/04 ,  Y02D10/13

Abstract: Aspects disclosed herein relate to techniques and an efficient architecture for enabling multi-way reads on highly associative content addressable memory (CAM) arrays. For example, a method for performing a tag search of a tag array can include reading a first subset of stored tag bits from multiple entries of the tag array, and comparing a second subset of stored tag bits from a one or more entries of the tag array against a search-tag to produce one or more possible way hit signals.