公开(公告)号：US11705091B2

公开(公告)日：2023-07-18

申请号：US17449630

申请日：2021-09-30

Applicant: QUALCOMM Incorporated

Inventor： Sushil Chauhan ,  Mahesh Aia ,  Dileep Marchya

IPC: G09G5/377 ,  G06T1/20

CPC classification number: G09G5/377 ,  G06T1/20 ,  G09G2360/18

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for parallelization of GPU composition with DPU topology selection. A processor may receive an indication of a plurality of application layers for composition at a first processor (e.g., a DPU) and a second processor (e.g., a GPU). The processor may select one or more first application layers of the plurality of application layers for attempted composition at the first processor and one or more second application layers of the plurality of application layers for composition at the second processor. The processor may transmit each of the one or more first application layers to the first processor for composition and each of the one or more second application layers to the second processor for composition.

公开(公告)号：US11200866B1

公开(公告)日：2021-12-14

申请号：US17176767

申请日：2021-02-16

Applicant: QUALCOMM Incorporated

Inventor： Dileep Marchya ,  Sudeep Ravi Kottilingal ,  Srinivas Pullakavi ,  Dhaval Kanubhai Patel ,  Prashant Nukala ,  Nagamalleswararao Ganji ,  Mohammed Naseer Ahmed ,  Mahesh Aia ,  Kalyan Thota ,  Sushil Chauhan

IPC: G06T1/20 ,  G06T1/60 ,  G09G5/00

Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

公开(公告)号：US20250086746A1

公开(公告)日：2025-03-13

申请号：US18466498

申请日：2023-09-13

Applicant: QUALCOMM Incorporated

Inventor： Srinivas Pullakavi ,  Dileep Marchya ,  Padmanabhan Komanduru V ,  Mahesh Aia ,  Dhaval Kanubhai Patel ,  Kalyan Thota ,  Sumit Gemini

IPC: G06T1/20 ,  G06F3/147

Abstract: Optimizing compositor workload in steady state in processor devices is disclosed herein. In some aspects, a processor device is configured to perform image compositing by executing a compositor pipeline that comprises a compositor including a workload handler; a composer Hardware Abstraction Layer (HAL); a workload governor communicatively coupled to the composer HAL; and a display driver. The workload governor detects that the image compositing has entered a steady state, and transmits an indication to enter an accelerated mode to the workload handler. Upon receiving the indication, the workload handler places the compositor pipeline in the accelerated mode. While in the accelerated mode, the compositor transmits accelerated mode data directly to the display driver, bypassing the composer HAL.

公开(公告)号：US12033603B2

公开(公告)日：2024-07-09

申请号：US17110200

申请日：2020-12-02

Applicant: QUALCOMM Incorporated

Inventor： Mahesh Aia ,  Mohammed Naseer Ahmed

IPC: G09G5/377 ,  G06T1/20

CPC classification number: G09G5/377 ,  G06T1/20 ,  G09G2340/125

Abstract: The present disclosure relates to methods and devices for display processing including an apparatus, e.g., a DPU, a compositor, a compositor backend, a DPU driver, and/or DPU firmware. In some aspects, the apparatus may receive content information for each of one or more layers of a frame. The apparatus may also determine whether the content information for each of the one or more layers includes at least one priority format. Additionally, the apparatus may determine a priority order of the one or more layers when the content information for at least one of the one or more layers includes at least one priority format. The apparatus may also map each of one or more display overlay resources to each of the one or more layers based on the determined priority order of the one or more layers.