公开(公告)号：US20160163443A1

公开(公告)日：2016-06-09

申请号：US14743623

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Mete ERTURK ,  Ravindra Vaman SHENOY ,  Kwan-yu LAI ,  Jitae KIM ,  Donald William KIDWELL JR. ,  Jon Bradley LASITER ,  James Thomas DOYLE ,  Omar James BCHIR

IPC: H01F27/28 ,  H01F41/14 ,  H05K1/18 ,  H01F41/02 ,  H05K1/11 ,  H01F27/24 ,  H01F1/147

CPC classification number: H01F27/2804 ,  H01F1/14708 ,  H01F5/00 ,  H01F17/0033 ,  H01F27/24 ,  H01F41/02 ,  H01F41/046 ,  H01F41/14 ,  H01F2017/002 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/165 ,  H05K1/182 ,  H05K2201/10166 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract translation: 电感器可以包括第一衬底，磁片和导体。 第一基板可以形成在第二基板内。 磁片可以连接到第一衬底的第一侧。 导体可以形成在第二基板内，第二基板上，或两者上。 导体可以具有输入和输出。 导体可以被配置为围绕第一基板而不与第一基板接触并且不与磁片接触。

公开(公告)号：US20160315024A1

公开(公告)日：2016-10-27

申请号：US14691946

申请日：2015-04-21

Applicant: QUALCOMM Incorporated

Inventor： Kwan-yu LAI ,  Ravindra Vaman SHENOY ,  Urmi RAY

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L2224/04105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2224/81805 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit package includes a core such as a thin glass core with through-core vias. A photo-patternable material is disposed directly on surfaces of the core and in the through-core vias and is selectively patterned to expose at least an exposed portion of the surface of the core and the through-core vias. A metal layer, such as copper, is disposed in the exposed portion of the core and in the through-core vias. A mechanical handler frame may be used to clamp together the various layers including the core and the photo-patternable material. The photo-patternable material that remains after patterning is permanent, and prevents the mechanical handler frame from directly contacting the core. Thus the photo-patternable material provides mechanical support to the core and protects the core from the mechanical handler.

Abstract translation: 集成电路封装包括芯，例如具有贯通芯通孔的薄玻璃芯。 光可图案化材料直接设置在芯的表面和通孔通孔中，并且被选择性地图案化以暴露核心表面和透核通孔的至少暴露部分。 金属层，例如铜，被布置在芯的暴露部分和通孔通孔中。 可以使用机械处理器框架将包括芯和可光图案化材料的各种层夹在一起。 在图案化之后保留的可光图案的材料是永久性的，并且防止机械处理器框架直接接触芯部。 因此，可照光图案材料为芯提供机械支撑并且保护芯不受机械处理器的影响。

公开(公告)号：US20150311271A1

公开(公告)日：2015-10-29

申请号：US14451462

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Mete ERTURK ,  Ravindra Vaman SHENOY ,  Kwan-yu LAI ,  Donald William KIDWELL, JR. ,  Jitae KIM ,  Jon Bradley LASITER

IPC: H01L49/02 ,  H01F27/24

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/24 ,  H01F2017/004 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/12105 ,  H01L2924/18162 ,  H01L2924/19042

Abstract: One or more high-inductance, high-quality factor (Q) three-dimensional inductors, for example, solenoid or toroid inductors with small form factors, are provided in an integrated circuit package, such as an integrated fanout package.

Abstract translation: 一个或多个高感度，高品质因子（Q）三维电感器，例如具有小形状因数的螺线管或环形电感器，被提供在集成电路封装中，例如集成扇出封装。