公开(公告)号：US20160293234A1

公开(公告)日：2016-10-06

申请号：US14742706

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Stephen Edward LILES ,  Satendra Kumar MAURYA ,  Kunal GARG ,  Chiaming CHAI ,  Chintan SHAH

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066

Abstract: An asynchronous memory includes a memory array, a sense amplifier, an output latch, and a controller. In response to a clock signal from an external circuit requesting a read operation, the controller provides the clock signal to the memory array to read data, and controls the sense amplifier and the output latch to provide the functionality of a flip-flop master and slave so that the read operation delay through the output latch to the external circuit is removed from a first read cycle of two sequential read cycles.

Abstract translation: 异步存储器包括存储器阵列，读出放大器，输出锁存器和控制器。 响应于来自外部电路的请求读取操作的时钟信号，控制器将时钟信号提供给存储器阵列以读取数据，并且控制读出放大器和输出锁存器以提供触发器主器件和从器件的功能 使得通过输出锁存器到外部电路的读操作延迟从两个顺序读周期的第一读周期中去除。