Abstract:
Aspects of a wireless apparatus and a method for handling a modulated signal include a frequency generator that produces a clock signal, a first synchronization circuit that generates a first sync enable signal based on an even edge of the clock signal, a second synchronization circuit that generates a second sync enable signal based on an even edge of the clock signal, a first divider having a first initial operating condition that generates a first IQ path based on the first sync enable signal, and a second divider having a second initial operating condition that generates a second IQ path based on the second sync enable signal, wherein the first and second operating conditions are not equal when initially powered.
Abstract:
Systems, apparatus and methods in a mobile device to multiplex two global navigation satellite system (GNSS) signals on a single hardware receiver chain are presented. The GNSS signals may come from a common GNSS system on two bands of two different GNSS systems overlapping on a common band. A duty cycle of the GNSS signals may be based on a harmonic being within one of the first band and the second band. The duty cycle may be based on signal quality, such as indicating a jammed or non jammed signal. The duty cycle may be of unequal proportions and less than 100% such that the receiver chain is idle for a percentage of time.
Abstract:
Certain aspects of the present disclosure are directed towards an apparatus for power management. The apparatus generally includes a switch and logic configured to: receive an input to configure the apparatus in a deep sleep mode; and open the switch to turn off power from a voltage rail to at least one first circuit having leakage current that is greater than a threshold, wherein at least one second circuit having leakage current less than the threshold is coupled to the voltage rail.
Abstract:
Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.
Abstract:
Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.
Abstract:
An advantageously fast and asynchronous interface is disclosed for the tuning of an RF frontend. The interface transmits a tuning word to the RF frontend that controls a tuning of the RF frontend responsive to a channel index.
Abstract:
Certain aspects of the present disclosure provide methods and apparatus for generating a two-tone signal for performing linearity calibration of a radio frequency (RF) circuit. One example apparatus generally includes a tone generating circuit configured to generate a first single-tone signal from a digital clock signal and a mixer connected with the tone generating circuit and configured to mix the first single-tone signal with a second single-tone signal to provide a two-tone signal having frequencies at a sum and a difference of frequencies of the first and second single-tone signals.