Low-power clocking for a high-speed memory interface

    公开(公告)号:US10169262B2

    公开(公告)日:2019-01-01

    申请号:US15204755

    申请日:2016-07-07

    Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

    LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE
    2.
    发明申请
    LOW-POWER CLOCKING FOR A HIGH-SPEED MEMORY INTERFACE 审中-公开
    用于高速存储器接口的低功耗时钟

    公开(公告)号:US20170017587A1

    公开(公告)日:2017-01-19

    申请号:US15204755

    申请日:2016-07-07

    Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.

    Abstract translation: 公开了在自适应通信接口中使用的方法,装置和系统。 提供了一种自适应通信接口,其中在低功率操作模式中抑制了以高速操作模式提供的高速时钟。 在低功耗操作模式下,低速指令基座用于存储器件与片上系统,应用处理器或其他器件之间的数据传输。 用于操作自适应通信接口的方法可以包括使用第一时钟信号来通过命令总线控制对存储器设备的命令的传输。 在第一操作模式中,第一时钟信号控制通过自适应通信接口的数据传输。 在第二种操作模式中,第二时钟信号通过自适应通信接口控制数据传输。 第二时钟信号的频率可以大于第一时钟信号的频率。

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