公开(公告)号：US20170363573A1

公开(公告)日：2017-12-21

申请号：US15186409

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Vladimir APARIN ,  Bo SUN ,  Joung Won PARK

IPC: G01N27/414 ,  G01N27/417

CPC classification number: G01N27/4145 ,  G01N27/27 ,  G01N27/417 ,  G01N33/48721

Abstract: An ionic current sensor array includes a master bias generator and a plurality of sensing cells. The master bias generator is configured to generate a bias voltage. Each sensing cell includes an ionic current sensor, an integrating capacitor, a sense transistor coupled between the integrating capacitor and the ionic current sensor, and an amplifier coupled to provide a reference voltage to bias the ionic current sensor. The amplifier includes a first transistor and a second transistor. The first transistor is coupled to receive the bias voltage, and the second transistor is coupled to the first transistor to provide the reference voltage to the ionic current sensor. The second transistor is also coupled between a source of the sense transistor and the gate of the sense transistor.

公开(公告)号：US20230087145A1

公开(公告)日：2023-03-23

申请号：US17481666

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Jianwen YE ,  Bo SUN ,  Cheng ZHONG

IPC: H03K5/00 ,  H03K5/01 ,  H03K19/20 ,  H03L7/081 ,  H04B1/40 ,  H04L12/40

Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

公开(公告)号：US20180149680A1

公开(公告)日：2018-05-31

申请号：US15362762

申请日：2016-11-28

Applicant: QUALCOMM Incorporated

Inventor： Bo SUN ,  Joung Won PARK

IPC: G01R19/00 ,  G01R15/16 ,  C12Q1/68

CPC classification number: G01R19/0061 ,  C12Q1/6869 ,  G01N33/48728 ,  C12Q2565/631

Abstract: A sensing cell includes a current sensor, an integrating capacitor, and a voltage buffer. The integrating capacitor is configured to store a voltage representative of a current signal generated by the current sensor. The voltage buffer is coupled to provide a buffered voltage to a readout line and includes a first transistor and a second transistor. The first transistor is coupled to receive the voltage stored on the integrating capacitor and the second transistor is coupled to the readout line. The second transistor is configured to compensate for a body effect of the first transistor.

公开(公告)号：US20190326862A1

公开(公告)日：2019-10-24

申请号：US15956026

申请日：2018-04-18

Applicant: QUALCOMM Incorporated

Inventor： Bo SUN ,  Yi TANG ,  Daniel BUTTERFIELD

IPC: H03F1/56 ,  H03F1/02

Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.

公开(公告)号：US20170310458A1

公开(公告)日：2017-10-26

申请号：US15269320

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Marco ZANUSO ,  Giovanni MARUCCI ,  Tsai-Pi HUNG ,  Francesco GATTA ,  Bo SUN

IPC: H04L7/033 ,  H04W72/04 ,  H04B1/40

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.