公开(公告)号：US09658671B2

公开(公告)日：2017-05-23

申请号：US15173004

申请日：2016-06-03

Applicant: QUALCOMM Incorporated

Inventor： Harshit Tiwari ,  Akshay Kumar Gupta ,  Srinivas Turaga ,  Deva Sudhir Kumar Pulivendula ,  Venkata Devarasetty

IPC: G11C5/14 ,  G06F1/26 ,  G06F12/0811

CPC classification number: G06F1/266 ,  G06F1/32 ,  G06F12/0811 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2213/0038 ,  G11C5/14

Abstract: A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.