公开(公告)号：US20220035437A1

公开(公告)日：2022-02-03

申请号：US16944070

申请日：2020-07-30

Applicant: QUALCOMM Incorporated

Inventor： Venkatesh RAVIPATI ,  Venkata Biswanath DEVARASETTY ,  Nirav Narendra DESAI ,  Lakshmi Narayana PANUKU ,  Kumar Kanti GHOSH ,  Sharath Kumar NAGILLA ,  Sravan Kumar Ambapuram ,  Shrikanth Shenoy

IPC: G06F1/3296

Abstract: An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

公开(公告)号：US20230401156A1

公开(公告)日：2023-12-14

申请号：US17806291

申请日：2022-06-10

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0891 ,  G06F12/0895 ,  G06F12/123

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/124

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

公开(公告)号：US20240061490A1

公开(公告)日：2024-02-22

申请号：US17891893

申请日：2022-08-19

Applicant: QUALCOMM INCORPORATED

Inventor： Karthik RANGARAJU ,  Sumit GEMINI ,  Nikhil Kumar KANSAL ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY ,  Lakshmi Narayana PANUKU ,  Venkatesh RAVIPATI

IPC: G06F1/3228 ,  G06F9/50 ,  H04M3/22

CPC classification number: G06F1/3228 ,  G06F9/5033 ,  H04M3/2227

Abstract: Systems, methods and computer-readable mediums may be used in portable computing devices (PCDs) for dynamically allocating system resources in a way that prevents or lessens degradation of power and performance KPIs while also avoiding temperature increases in the PCD that can create unpleasant user experiences. A smart resource allocation framework (SRAF) is triggered when a call is received or placed. Once triggered, the SRAF framework monitors a preselected set of state conditions to determine whether or not to place the wireless modem in a modem power-performance (Mod. Pow.-Perf) mode. If it determines that modem is to be placed in the Mod. Pow.-Perf. mode, a Mod. Pow.-Perf. process is performed dynamically allocates system resources and preferably also triggers a thermal framework that performs power reduction in one or more non-modem processing cores.

公开(公告)号：US20250103479A1

公开(公告)日：2025-03-27

申请号：US18475492

申请日：2023-09-27

Applicant: QUALCOMM Incorporated

Inventor： Shriharsha CHEBBI ,  Nirav Narendra DESAI ,  Badrinath DORAIRAJAN ,  Lakshmi Narayana PANUKU

IPC: G06F12/02 ,  G06F12/0891

Abstract: Various embodiments include systems and methods for improving Dynamic Random-Access Memory (DRAM) efficiency and Last Level Cache (LLC) utilization. A computing system may be configured to dynamically adjust DRAM efficiency calculations based on multiple system metrics and conditions (e.g., DDR frequency, density, refresh rates, etc.) for more accurate frequency settings and improved power consumption. The computing system may use a multi-stage approach that includes memory and cache allocation, bandwidth management, and frequency settings. The computing system may fine-tune the DRAM efficiency calculations based on various other factors (e.g., cache miss rates, power consumption, etc.), dynamically modify operational parameters (e.g., DDR frequencies, etc.) in response to specific events or computational tasks, and work in tandem with other system components (e.g., a Last-Level Cache Controller (LLCC), etc.) to improve resource allocation.

公开(公告)号：US20230401152A1

公开(公告)日：2023-12-14

申请号：US17827302

申请日：2022-05-27

Applicant: QUALCOMM Incorporated

Inventor： Hithesh Hassan LEPAKSHA ,  Sharath Kumar NAGILLA ,  Darshan Kumar NANDANWAR ,  Nirav Narendra DESAI ,  Venkata Biswanath DEVARASETTY

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/468

Abstract: Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.