公开(公告)号：US20200303094A1

公开(公告)日：2020-09-24

申请号：US16800949

申请日：2020-02-25

Applicant: QUALCOMM Incorporated

Inventor： Harikrishna CHINTARLAPALLI REDDY ,  Alvin Leng Sun LOKE

IPC: H01C1/01 ,  H01L27/01

Abstract: An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

公开(公告)号：US20210287829A1

公开(公告)日：2021-09-16

申请号：US17334402

申请日：2021-05-28

Applicant: QUALCOMM INCORPORATED

Inventor： Harikrishna CHINTARLAPALLI REDDY ,  Alvin Leng Sun LOKE

IPC: H01C1/01 ,  H01L27/01

Abstract: An apparatus including a dielectric layer; and a set of thin-film resistors arranged in a row extending in a first direction on the dielectric layer, wherein lengths of the set of thin-film resistors in a second direction substantially orthogonal to the first direction are substantially the same, wherein the set of thin-film resistors includes a first subset of one or more thin-film resistors with respective terminals spaced apart by a first distance, and wherein the set of thin-film resistors includes a second subset of one or more thin-film resistors with respective terminals spaced apart by a second distance, the first distance being different than the second distance.

公开(公告)号：US20190304905A1

公开(公告)日：2019-10-03

申请号：US15992473

申请日：2018-05-30

Applicant: QUALCOMM Incorporated

Inventor： Tin Tin WEE ,  Alvin Leng Sun LOKE ,  Jacob SCHNEIDER

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L49/02 ,  H01L27/06

Abstract: Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias.