公开(公告)号：US20230362498A1

公开(公告)日：2023-11-09

申请号：US18353801

申请日：2023-07-17

Applicant: Postech Research and Business Development Foundation

Inventor： Hyungjun KIM ,  Yulhwa KIM ,  Sungju RYU ,  Jae-Joon KIM

IPC: H04N23/84 ,  G06T7/00

CPC classification number: H04N23/84 ,  G06T7/97 ,  G06T2207/20084 ,  G06T2207/20221

Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.

公开(公告)号：US20210027142A1

公开(公告)日：2021-01-28

申请号：US16933889

申请日：2020-07-20

Applicant: Postech Research and Business Development Foundation

Inventor： Hyungjun KIM ,  Yulhwa KIM ,  Sungju RYU ,  Jae-Joon KIM

IPC: G06N3/04 ,  G06N3/08 ,  G06T1/20

Abstract: Disclosed is a method of operating a neural network system. The method includes splitting input feature data into first splitting data corresponding to a first digit bit and second splitting data corresponding to a second digit bit different from the first digit bit, propagating the first splitting data through a first binary neural network, propagating the second splitting data through a second binary neural network, and merging first result data by propagation of the first splitting data and second result data by propagating the second splitting data to generate output feature data.

公开(公告)号：US20210074349A1

公开(公告)日：2021-03-11

申请号：US17011929

申请日：2020-09-03

Applicant: Postech Research and Business Development Foundation

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418 ,  G06N3/08

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

公开(公告)号：US20200160160A1

公开(公告)日：2020-05-21

申请号：US16687599

申请日：2019-11-18

Applicant: POSTECH Research and Business Development Foundation

Inventor： Jae-Joon KIM ,  Hyungjun KIM ,  Yulhwa KIM

IPC: G06N3/063 ,  G11C11/54 ,  G11C13/00 ,  G06N3/04

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

公开(公告)号：US20220246204A1

公开(公告)日：2022-08-04

申请号：US17723358

申请日：2022-04-18

Applicant: Postech Research and Business Development Foundation

Inventor： Jinseok KIM ,  Yulhwa KIM ,  Jae-Joon KIM ,  Hyungjun KIM

IPC: G11C11/412 ,  G06N3/08 ,  G11C11/418 ,  G11C11/419

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.