公开(公告)号：US20030168150A1

公开(公告)日：2003-09-11

申请号：US10224949

申请日：2002-08-20

申请人： Phycomp Taiwan Ltd

发明人： Wen-Hsi Lee ,  Che-Yi Su ,  Chun-Te Lee ,  Jui-Chu Jao

IPC分类号： C03B029/00

CPC分类号： B32B18/00 ,  B32B38/145 ,  B32B2038/042 ,  B32B2315/02 ,  C04B2235/3239 ,  C04B2235/36 ,  C04B2235/365 ,  C04B2235/9615 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/50 ,  C04B2237/56 ,  C04B2237/562 ,  C04B2237/62 ,  C04B2237/702 ,  C04B2237/704 ,  H01L21/4857 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/4611 ,  H05K3/4629

摘要： The present invention mainly relates to a method for reducing X-Y shrinkage during sintering low temperature ceramic comprising piling a constrain layer on a dielectric layer on a green ceramic body, which is printed with heterogeneous materials for conductors, resistors, capacitors and the like and/or disposed conductors, resistors, capacitors and the like to reduce shrinkage of the dielectric layer and the green ceramic body. The invention is characterized in that the constrain layer comprises windows in positions complying with the heterogeneous materials and/or conductors, resistors, capacitors and the like printed and/or disposed on the dielectric layer and the green ceramic body to make the heterogeneous materials and/or conductors, resistors, capacitors and the like not being covered when piling the constrain layer and the dielectric layers of the green ceramic body.

摘要翻译： 本发明主要涉及一种减少烧结低温陶瓷中XY收缩的方法，包括在生陶瓷体上的电介质层上堆叠约束层，该陶瓷体上印有用于导体，电阻器，电容器等的异种材料和/或 布置导体，电阻器，电容器等，以减小电介质层和生坯陶瓷体的收缩。 本发明的特征在于，约束层包括在符合非均质材料的位置的窗口和/或印刷和/或设置在电介质层和生坯陶瓷体上的导体，电阻器，电容器等，以使异质材料和/ 或者在对生陶瓷体的约束层和电介质层进行打桩时不会覆盖导体，电阻器，电容器等。