公开(公告)号：US4670839A

公开(公告)日：1987-06-02

申请号：US425022

申请日：1982-09-27

Applicant: John F. Pilat ,  Thomas M. Jones ,  James T. Nealon ,  Gary Davidian ,  Paul Bowden

Inventor： John F. Pilat ,  Thomas M. Jones ,  James T. Nealon ,  Gary Davidian ,  Paul Bowden

IPC: G06F9/318 ,  G06F9/355 ,  G06F12/10 ,  G06F9/10

CPC classification number: G06F9/30192 ,  G06F12/1036 ,  G06F9/30167 ,  G06F9/355

Abstract: Encachement apparatus consisting of first and second caches responsive to first and second keys, respectively, for outputting first and second data therefrom. In one embodiment, the second cache which includes a stack having a plurality of frames, outputs data contained in a current frame thereof in response to a second key which is obtained from the first cache. The data outputted from each cache is received substantially simultaneously at a combiner which combines such data to produce the desired third data from the dual cache system.

Abstract translation: 包括分别响应于第一和第二键的第一和第二高速缓冲存储器，用于从其输出第一和第二数据的加密装置。 在一个实施例中，包括具有多个帧的堆栈的第二高速缓存响应于从第一高速缓存获得的第二密钥输出包含在当前帧中的数据。 从组合器基本上同时接收从每个高速缓冲存储器输出的数据，该组合器组合了这样的数据以从双缓存系统产生期望的第三数据。

公开(公告)号：US4471430A

公开(公告)日：1984-09-11

申请号：US425028

申请日：1982-09-27

Applicant: Paul Bowden ,  Gary Davidian

Inventor： Paul Bowden ,  Gary Davidian

IPC: G06F12/10 ,  G06F13/00

CPC classification number: G06F12/1036

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache. The control apparatus responds to the base specifier by causing the first multiplexer to select the displacement value output by the cache and causing the second multiplexer to select one of the values contained in the registers or the value output by the second cache in response to the second displacement. The adder then adds the value selected by the first multiplexer to the value selected by the second multiplexer and outputs the result.

公开(公告)号：US4428045A

公开(公告)日：1984-01-24

申请号：US301998

申请日：1981-09-11

Applicant: Gary Davidian

Inventor： Gary Davidian

IPC: G06F9/35 ,  G06F12/02 ,  G06F1/00 ,  G06F9/00

CPC classification number: G06F9/30167 ,  G06F12/0292 ,  G06F9/35

Abstract: Improved apparatus for specifying and resolving addresses of operands in a digital data processing system. Instructions executed by the system are contained in procedures. Addresses are calculated using a set of architectural base addresses. Operands are represented in the instructions by means of names. The names include immediate names, which directly specify one of the architectural base registers and a displacement, and table names, which specify a name table entry in a name table associated with the procedure. The name table entry specifies how the address of the operand represented by the table name may be derived using the architectural base addresses and information contained in the name table. Each name table entry includes a basic name table entry. The basic name table entry contains a base source specifier and a base or displacement specifier. The base source specifier specifies either one of the architectural base addresses as a base address or that the base address is not one of the architectural base addresses. In the former case, the base or displacement specifier specifies a displacement; in the latter, it contains an immediate name or a table name specifying another name table entry in the name table and the base address is derived using the immediate name or table name. Calculation of addresses is performed by name processing apparatus which is responsive to the base source specifier and the base or displacement specifier.

Abstract translation: 用于指定和解析数字数据处理系统中的操作数的地址的改进的装置。 系统执行的指令包含在程序中。 地址使用一组架构基地址计算。 操作数通过名称在指令中表示。 这些名称包括立即名称，它们直接指定一个架构基础寄存器和一个位移，以及表名称，它们在与该过程相关联的名称表中指定名称表项。 名称表条目指定如何使用名称表中包含的体系结构基址和信息来导出由表名称表示的操作数的地址。 每个名称表项包含一个基本名称表项。 基本名称表条目包含基本源说明符和基本位移说明符。 基础源说明符指定架构基地址之一作为基地址，或者基地址不是架构基地址之一。 在前一种情况下，基础或位移说明符指定位移; 在后者中，它包含立即名称或表名，在名称表中指定另一个名称表项，并使用立即名称或表名导出基址。 地址的计算由响应于基本源说明符和基地或位移说明符的名称处理装置执行。

公开(公告)号：US4473881A

公开(公告)日：1984-09-25

申请号：US425029

申请日：1982-09-27

Applicant: John F. Pilat ,  Thomas M. Jones ,  James T. Nealon ,  Gary Davidian

Inventor： John F. Pilat ,  Thomas M. Jones ,  James T. Nealon ,  Gary Davidian

IPC: G06F12/10 ,  G06F13/00

CPC classification number: G06F12/1036

Abstract: Encachement apparatus consisting of a first cache, a second cache connected to the first cache, registers for storing data, an adder receiving inputs from a first multiplexer connected to the first cache and a second multiplexer connected to the second cache and to the registers, and control apparatus connected to the first cache, the first multiplexer, and the second multiplexer. The first cache outputs a cache entry in response to a key. The cache entry contains a first displacement value, a base specifier specifying either one of the registers or the second cache, and in the case of entries specifying the second cache, a second displacement value. The first displacement value is output to the first multiplexer, the base specifier is output to the control apparatus, and the second displacement, if present, is output to the second cache. The control apparatus responds to the base specifier by causing the first multiplexer to select the displacement value output by the cache and causing the second multiplexer to select one of the values contained in the registers or the value output by the second cache in response to the second displacement. The adder then adds the value selected by the first multiplexer to the value selected by the second multiplexer and outputs the result.

公开(公告)号：US4450523A

公开(公告)日：1984-05-22

申请号：US302264

申请日：1981-09-11

Applicant: John F. Pilat ,  Anastasia J. Czerniakiewicz ,  David B. Kinder ,  Gary Davidian

Inventor： John F. Pilat ,  Anastasia J. Czerniakiewicz ,  David B. Kinder ,  Gary Davidian

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/34

CPC classification number: G06F9/30192 ,  G06F9/3016 ,  G06F9/35

Abstract: Improved apparatus for specifying and computing the current length of varying-length data items, together with methods for computing the current length. The apparatus and methods are used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The name table entry associated with the name represented by the varying-length data item includes a current number of elements item specifier specifying the address of a current number of elements item which specifies the number of elements currently in the represented varying-length data item. The name table entry further includes an element size specifier specifying the size of the elements. A name processor in the processor uses the current number of elements item specifier to obtain the the address of the current number of elements item and and fetches the current number of elements item from memory. The name translator then calculates the current length using the element size and the current number of elements item.

Abstract translation: 用于指定和计算变长数据项的当前长度的改进的装置，以及用于计算当前长度的方法。 该装置和方法用于数字计算机系统，其中数据项由与存储器中的名称表输入项相关联的名称表示。 与由变长数据项表示的名称相关联的名称表条目包括指定当前数量的元素项目的地址的元素项目说明符的当前数量项目，其指定当前在所表示的变长数据项目中的元素的数量。 名称表条目还包括指定元素大小的元素大小说明符。 处理器中的名称处理器使用当前数量的元素项说明符来获取当前元素数量项的地址，并从内存中获取当前元素数。 名称翻译器然后使用元素大小和当前元素数量来计算当前长度。