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公开(公告)号:US12255127B2
公开(公告)日:2025-03-18
申请号:US17190261
申请日:2021-03-02
Inventor: Hidekazu Nakamura , Manabu Yanagihara , Tomohiko Nakamura , Yusuke Katagiri , Katsumi Otani , Takeshi Kawabata
Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.
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公开(公告)号:US11189549B2
公开(公告)日:2021-11-30
申请号:US16363828
申请日:2019-03-25
Inventor: Hidekazu Nakamura , Manabu Yanagihara , Tomohiko Nakamura , Yusuke Katagiri , Katsumi Otani , Takeshi Kawabata
Abstract: A semiconductor device that is a surface mount-type device includes a nitride semiconductor chip including a silicon substrate having a first thermal expansion coefficient and an InxGayAl1-x-yN layer in contact with a surface of the silicon substrate, where 0≤x≤1, 0≤y≤1, 0≤x+y≤1; and a die pad including Cu and having a second thermal expansion coefficient that is greater than the first thermal expansion coefficient. A thickness of the nitride semiconductor chip is at least 0.2 mm, length L of the nitride semiconductor chip is at least 3.12 mm, and thickness tm of the die pad and length L of the nitride semiconductor chip satisfy tm≥2.00×10−3×L2+0.173, tm being a thickness in mm and L being a length in mm.
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公开(公告)号:US10305008B2
公开(公告)日:2019-05-28
申请号:US15787408
申请日:2017-10-18
Inventor: Takeshi Kawabata , Kiyomi Hagihara , Satoshi Kanai , Takashi Yui
Abstract: A semiconductor module includes: one or more semiconductor elements; a wiring substrate having a first surface on which the one or more semiconductor elements are mounted, the wiring substrate being electrically connected to the one or more semiconductor elements; a heat sink on which the wiring substrate is mounted, the heat sink facing a second surface of the wiring substrate on a reverse side of the first surface; a binder which is formed in a die pad area on the heat sink so as to be present between the wiring substrate and the heat sink, and bonds the wiring substrate and the heat sink; and a support which is formed in a peripheral part of the die pad area on the heat sink, and fixes the wiring substrate to the heat sink by being in contact with a peripheral part of the second surface of the wiring substrate.
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