公开(公告)号：US09666664B2

公开(公告)日：2017-05-30

申请号：US14663140

申请日：2015-03-19

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Ryo Kajitani ,  Tetsuzo Ueda ,  Yoshiharu Anda ,  Naohiro Tsurumi ,  Satoshi Nakazawa

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/0611 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/51 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78

Abstract: An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.