公开(公告)号：US20120025268A1

公开(公告)日：2012-02-02

申请号：US13253692

申请日：2011-10-05

Applicant: Osamu ICHIKAWA

Inventor： Osamu ICHIKAWA

IPC: H01L29/267 ,  H01L21/20

CPC classification number: H01L27/0605 ,  H01L21/8252 ,  H01L29/7371 ,  H01L29/7785 ,  H01L29/7786

Abstract: There is provided a compound semiconductor wafer that is suitably used as a semiconductor wafer to form a plurality of different types of devices such as an HBT and an FET thereon. The semiconductor wafer includes a first semiconductor, a carrier-trapping layer that is formed on the first semiconductor and has an electron-trapping center or a hole-trapping center, a second semiconductor that is epitaxially grown on the carrier-trapping layer and serves as a channel in which a free electron or a free hole moves, and a third semiconductor including a stack represented by n-type semiconductor/p-type semiconductor/n-type semiconductor or represented by p-type semiconductor/n-type semiconductor/p-type semiconductor, where the stack epitaxially grown on the second semiconductor.

Abstract translation: 提供了适合用作半导体晶片以形成诸如HBT和FET之类的多种不同类型的器件的化合物半导体晶片。 半导体晶片包括第一半导体，形成在第一半导体上并具有电子俘获中心或空穴俘获中心的载流子俘获层，在载流子俘获层上外延生长的第二半导体，用作 由n型半导体/ p型半导体/ n型半导体表示的或由p型半导体/ n型半导体/ p型表示的第三半导体，其中自由电子或自由孔移动的沟道 型半导体，其中在第二半导体上外延生长的叠层。

公开(公告)号：US20090098349A1

公开(公告)日：2009-04-16

申请号：US11872145

申请日：2007-10-15

Applicant: Osamu ICHIKAWA

Inventor： Osamu ICHIKAWA

IPC: B32B3/10

CPC classification number: B29C45/14688 ,  B29C37/0032 ,  B29C45/14811 ,  B29C2037/0042 ,  B29C2045/14704 ,  B29K2715/006 ,  B29K2995/002 ,  B29K2995/0026 ,  B32B7/12 ,  B32B27/08 ,  B32B2255/10 ,  B32B2307/402 ,  B32B2307/412 ,  B44C1/1704 ,  C09D11/00 ,  Y10T428/24868 ,  Y10T428/24876 ,  Y10T428/24901 ,  Y10T428/2848 ,  Y10T428/2878

Abstract: There is provided a decorated sheet having a good adhesiveness with a molding resin regardless of a pattern of a colored part. A decorated sheet comprising: a transparent layer coating on the entire surface of a thermoplastic substrate sheet or at least in the areas of said substrate sheet having no coloring layer formed, said transparent layer coated by a transparent ink with as common varnish composition as the ink for coloring layer formation, and an adhesive layer formed as the outermost layer of said decorated sheet on the side provided with the colored layers of the substrate sheet. A molded article is fabricated by integrating the decorated sheet with a molding resin.

Abstract translation: 提供了与着色部件的图案无关地与模制树脂具有良好粘附性的装饰片材。 一种装饰片材，其包括：在热塑性基材片的整个表面上的至少在所述基片上形成的没有着色层的区域中的透明层涂层，所述透明层涂覆有作为墨水的普通清漆组合物的透明墨水 用于着色层形成，以及在设置有基板的着色层的一侧上形成为所述装饰片的最外层的粘合层。 通过将装饰的片材与模塑树脂整合来制造模制品。

公开(公告)号：US20120104462A1

公开(公告)日：2012-05-03

申请号：US13301279

申请日：2011-11-21

Applicant: Osamu ICHIKAWA

Inventor： Osamu ICHIKAWA

IPC: H01L27/06 ,  H01L21/20 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L21/0237 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02573 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/207 ,  H01L29/66462 ,  H01L29/812

Abstract: A semiconductor wafer includes a first semiconductor, and a second semiconductor formed directly or indirectly on the first semiconductor. The second semiconductor contains a first impurity atom exhibiting p-type or n-type conductivity, and a second impurity atom selected such that the Fermi level of the second semiconductor containing both the first and second impurity atoms is closer to the Fermi level of the second semiconductor containing neither the first impurity atom nor the second impurity atom, than the Fermi level of the second semiconductor containing the first impurity atom is. For example, the majority carrier of the second semiconductor is an electron, and the Fermi level of the second semiconductor containing the first and second impurity atoms is lower than the Fermi level of the second semiconductor containing the first impurity atom.

Abstract translation: 半导体晶片包括直接或间接地形成在第一半导体上的第一半导体和第二半导体。 第二半导体包含表现出p型或n型导电性的第一杂质原子，并且选择第二杂质原子，使得含有第一和第二杂质原子的第二半导体的费米能级更接近第二杂质原子的费米能级 不含第一杂质原子和第二杂质原子的半导体比包含第一杂质原子的第二半导体的费米能级低。 例如，第二半导体的多数载流子是电子，含有第一和第二杂质原子的第二半导体的费米能级低于含有第一杂质原子的第二半导体的费米能级。

公开(公告)号：US20080215946A1

公开(公告)日：2008-09-04

申请号：US12098987

申请日：2008-04-07

Applicant: Osamu ICHIKAWA

Inventor： Osamu ICHIKAWA

IPC: G01R31/3183 ,  G06F11/00

CPC classification number: G11C29/12015 ,  G11C29/36 ,  G11C2029/3602

Abstract: A semiconductor integrated circuit is provided which is capable of testing a high-speed memory at the actual operation speed of the memory, even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.

Abstract translation: 提供了一种半导体集成电路，其能够以存储器的实际操作速度测试高速存储器，即使在集成电路的内置自检电路的操作速度受到限制的情况下也是如此。 为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分， 第二个时钟的反相时钟，用于生成测试数据。 此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据， 从而将测试数据作为测试数据输入存储器。 第二个时钟的频率比第一个时钟的频率低四分之一或一半。