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公开(公告)号：US20170006207A1
公开(公告)日：2017-01-05
申请号：US14791018
申请日：2015-07-02
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen
CPC classification number: H04N5/2353 , H04N5/2355 , H04N5/35581 , H04N5/3765 , H04N5/378
Abstract: A system and method for high dynamic range (HDR) imaging includes writing a first, second, and third sub-frame to a memory at a first, second, and third readout time, respectively, the first, second, and third sub-frame being generated by a same first sub-array of the array of image pixels. Subsequent to the third readout time, the first, second, and third sub-frames are sent to an image signal processor. Also subsequent to the third readout time, a fourth sub-frame is sent to the image sensor. The fourth sub-frame is generated by the same first sub-array of the array of image pixels. The fourth sub-frame bypasses the memory by being sent from an analog-to-digital converter to the image signal processor without being written to the memory.
Abstract translation: 用于高动态范围（HDR）成像的系统和方法包括分别在第一，第二和第三读出时间将第一，第二和第三子帧写入存储器，第一，第二和第三子帧 由图像像素阵列的相同的第一子阵列生成。 在第三读出时间之后，将第一，第二和第三子帧发送到图像信号处理器。 此外，在第三读出时间之后，向图像传感器发送第四子帧。 第四子帧由图像像素阵列的相同的第一子阵列生成。 第四子帧通过从模数转换器发送到图像信号处理器而不会被写入存储器来绕过存储器。
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公开(公告)号：US20160316164A1
公开(公告)日：2016-10-27
申请号：US14696120
申请日：2015-04-24
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen , Min Qu , Hyunseok Lee
Abstract: Readout circuitry to readout an array of image sensor pixels includes readout units that include a plurality of analog-to-digital converters (“ADCs”), a plurality of blocks of Static Random-Access Memory (“SRAM”), and a plurality of blocks of Dynamic Random-Access Memory (“DRAM”). The plurality ADCs is coupled to readout analog image signals two-dimensional blocks of the array of image sensor pixels. The plurality of blocks of SRAM is coupled to receive digital image signals from the ADCs. The digital image signals are representative of the analog image signal readout from the two-dimensional block of pixels. The plurality of blocks of DRAM is coupled to the blocks of SRAM. Each block of SRAM is coupled to sequentially output the digital image signals to each of the blocks of DRAM. Each of the readout units are coupled to output the digital image signals as a plurality of Input/Output (“IO”) signals.
Abstract translation: 用于读出图像传感器像素阵列的读出电路包括：读出单元，其包括多个模数转换器（“ADC”），多个静态随机存取存储器块（“SRAM”），以及多个 动态随机存取存储器块（“DRAM”）。 多个ADC耦合到图像传感器像素阵列的读出模拟图像信号二维块。 多个SRAM块被耦合以从ADC接收数字图像信号。 数字图像信号表示从二维像素块读出的模拟图像信号。 DRAM的多个块耦合到SRAM块。 SRAM的每个块被耦合以顺序地将数字图像信号输出到DRAM的每个块。 每个读出单元被耦合以输出数字图像信号作为多个输入/输出（“IO”）信号。
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3.发明授权公开(公告)号：US09247162B2
公开(公告)日：2016-01-26
申请号：US14317059
申请日：2014-06-27
Applicant: OmniVision Technologies, Inc.
Inventor： Jie Shen , Tiejun Dai
CPC classification number: H04N5/3575 , H04N5/378
Abstract: A system for performing digital correlated double sampling in an image sensor includes a memory for storing most significant bits of the digital image data and reset data produced by an analog-to-digital convertor. The system further includes least significant bit latches for each of the digital image data and reset data. The most significant bits are recombined with the least significant bits in respective recombined latches for each of the digital image data and reset data. A correlated double sampling stage then performs correlated double sampling and stores the correlated double sampled data in memory.
Abstract translation: 用于在图像传感器中执行数字相关双重采样的系统包括用于存储数字图像数据的最高有效位的存储器和由模拟 - 数字转换器产生的复位数据。 该系统还包括用于每个数字图像数据和复位数据的最低有效位锁存器。 最高有效位与用于数字图像数据和复位数据中的每一个的相应重组锁存器中的最低有效位重新组合。 相关的双采样级然后执行相关双采样并将相关的双采样数据存储在存储器中。
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4.发明申请SYSTEM AND METHOD FOR DIGITAL CORRELATED DOUBLE SAMPLING IN AN IMAGE SENSOR 有权用于图像传感器中数字相关双重采样的系统和方法公开(公告)号：US20150381911A1
公开(公告)日：2015-12-31
申请号：US14317059
申请日：2014-06-27
Applicant: OmniVision Technologies, Inc.
Inventor： Jie Shen , Tiejun Dai
CPC classification number: H04N5/3575 , H04N5/378
Abstract: A system for performing digital correlated double sampling in an image sensor includes a memory for storing most significant bits of the digital image data and reset data produced by an analog-to-digital convertor. The system further includes least significant bit latches for each of the digital image data and reset data. The most significant bits are recombined with the least significant bits in respective recombined latches for each of the digital image data and reset data. A correlated double sampling stage then performs correlated double sampling and stores the correlated double sampled data in memory.
Abstract translation: 用于在图像传感器中执行数字相关双重采样的系统包括用于存储数字图像数据的最高有效位的存储器和由模拟 - 数字转换器产生的复位数据。 该系统还包括用于每个数字图像数据和复位数据的最低有效位锁存器。 最高有效位与用于数字图像数据和复位数据中的每一个的相应重组锁存器中的最低有效位重新组合。 相关的双采样级然后执行相关双采样并将相关的双采样数据存储在存储器中。
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公开(公告)号：US09654699B2
公开(公告)日：2017-05-16
申请号：US14791018
申请日：2015-07-02
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen
CPC classification number: H04N5/2353 , H04N5/2355 , H04N5/35581 , H04N5/3765 , H04N5/378
Abstract: A system and method for high dynamic range (HDR) imaging includes writing a first, second, and third sub-frame to a memory at a first, second, and third readout time, respectively, the first, second, and third sub-frame being generated by a same first sub-array of the array of image pixels. Subsequent to the third readout time, the first, second, and third sub-frames are sent to an image signal processor. Also subsequent to the third readout time, a fourth sub-frame is sent to the image sensor. The fourth sub-frame is generated by the same first sub-array of the array of image pixels. The fourth sub-frame bypasses the memory by being sent from an analog-to-digital converter to the image signal processor without being written to the memory.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09743025B2
公开(公告)日：2017-08-22
申请号：US14985116
申请日：2015-12-30
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen
CPC classification number: H04N5/3765 , H01L27/14634 , H04N5/2253 , H04N5/2254 , H04N5/2353 , H04N5/2355 , H04N5/35581 , H04N5/378
Abstract: Stacked chip imaging system comprising pixel array partitioned into pixel sub-arrays (PSAs) disposed in first semiconductor die and ADC circuitry including ADC circuits disposed in second semiconductor die. Each PSA is arranged into pixel groups. Each pixel group generates pixel data signals. Pixel array captures image data of first frame with first exposure time, second frame with second exposure time, third frame with third exposure time, and fourth frame with fourth exposure time. First, second, third and fourth exposure times are different. At least one of the pixel groups in each of the pixel sub-arrays is coupled to a different ADC circuit from pixels groups remaining in each of the pixel sub-arrays. ADC circuitry acquires the pixel data signals. For each frame, ADC circuits converts pixel data signal received from pixel groups respectively coupled thereto from analog to digital to generate ADC outputs. Other embodiments are also described.
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公开(公告)号：US09681083B2
公开(公告)日：2017-06-13
申请号：US14738744
申请日：2015-06-12
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen , Jizhang Shan
CPC classification number: H04N5/378 , H04N5/2357 , H04N5/3532 , H04N5/35581
Abstract: A method of detecting light-emitting diode (LED) light starts with a control circuitry generating a shutter signal that is transmitted to a pixel array to control image acquisition by the pixel array and to establish a set exposure time. The readout circuitry may then read out the image data from the pixel array that includes reading out the image data from a plurality of successive and overlapped frames having the set exposure time. The set exposure time may be the same for each of the frames. The successive and overlapped frames may be interlaced frames. Other embodiments are also described.
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8.发明申请公开(公告)号：US20170195604A1
公开(公告)日：2017-07-06
申请号：US14985116
申请日：2015-12-30
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jie Shen
CPC classification number: H04N5/3765 , H01L27/14634 , H04N5/2253 , H04N5/2254 , H04N5/2353 , H04N5/2355 , H04N5/35581 , H04N5/378
Abstract: Stacked chip imaging system comprising pixel array partitioned into pixel sub-arrays (PSAs) disposed in first semiconductor die and ADC circuitry including ADC circuits disposed in second semiconductor die. Each PSA is arranged into pixel groups. Each pixel group generates pixel data signals. Pixel array captures image data of first frame with first exposure time, second frame with second exposure time, third frame with third exposure time, and fourth frame with fourth exposure time. First, second, third and fourth exposure times are different. At least one of the pixel groups in each of the pixel sub-arrays is coupled to a different ADC circuit from pixels groups remaining in each of the pixel sub-arrays. ADC circuitry acquires the pixel data signals. For each frame, ADC circuits converts pixel data signal received from pixel groups respectively coupled thereto from analog to digital to generate ADC outputs. Other embodiments are also described.
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公开(公告)号：US09667895B2
公开(公告)日：2017-05-30
申请号：US14707572
申请日：2015-05-08
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Johannes Solhusvik , Howard E. Rhodes , Jie Shen
IPC: H04N5/374 , H04N5/3745
CPC classification number: H04N5/37457
Abstract: An image sensor includes a pixel array disposed in a first semiconductor die. The pixel array is partitioned into a plurality of pixel sub-arrays. Each one of the plurality of pixel sub-arrays is arranged into a plurality of pixel groups. Each one of the plurality of pixel groups is arranged into a p×q array of pixel cells. A plurality of readout circuits is disposed in a second semiconductor die. An interconnect layer is stacked between the first semiconductor die and the second semiconductor die. The interconnect layer includes a plurality of conductors. Each one of the plurality of pixel sub-arrays is coupled to a corresponding one of the plurality of readout circuits through a corresponding one of the plurality of conductors.
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公开(公告)号：US09652575B2
公开(公告)日：2017-05-16
申请号：US14246859
申请日：2014-04-07
Applicant: OmniVision Technologies, Inc.
Inventor： Jie Shen
IPC: G06F17/50 , H01L27/146
CPC classification number: G06F17/5072 , H01L27/14634 , H01L27/14636 , H01L27/1464
Abstract: A floorplan-optimized stacked image sensor and a method for designing the sensor are disclosed. A sensor layer includes multiple PSAs partitioned into PSA groups. A circuit layer includes multiple analog-to-digital converters each communicatively coupled to a different PSA. Each analog-to-digital converter (ADC) is semi-aligned to the PSA group associated with the PSA to which it is communicatively coupled. The floorplan of ADCs maximizes contiguous global-based space on the circuit layer uninterrupted by an ADC. The resulting circuit layer floorplan has one or more global-based spaces interleaved with one or more local-based spaces containing ADCs.
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