公开(公告)号：US11153478B2

公开(公告)日：2021-10-19

申请号：US17136311

申请日：2020-12-29

申请人： OLYMPUS CORPORATION

发明人： Yoshinobu Tanaka ,  Atsushi Ishihara ,  Yutaka Murata ,  Akira Ueno

IPC分类号： H04N5/232

摘要： An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

公开(公告)号：US20210120173A1

公开(公告)日：2021-04-22

申请号：US17136311

申请日：2020-12-29

申请人： OLYMPUS CORPORATION

发明人： Yoshinobu Tanaka ,  Atsushi Ishihara ,  Yutaka Murata ,  Akira Ueno

IPC分类号： H04N5/232

摘要： An image processing device includes: an image sensor; a data buffer; an imaging interface part configured to read image data from the image sensor, generate an imaging signal, and write the generated imaging signal to the data buffer; an imaging processor configured to read out the imaging signal written in the data buffer and perform image processing; a synchronization signal generator configured to generate a synchronization signal synchronized with the image sensor; and a clock frequency controller configured to control a clock frequency of a clock input to the imaging processor on the basis of the synchronization signal, wherein the clock frequency controller is configured to change the clock frequency after a start of a valid period of the synchronization signal.

公开(公告)号：US11943545B2

公开(公告)日：2024-03-26

申请号：US17164961

申请日：2021-02-02

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Yoshinobu Tanaka ,  Atsushi Ishihara ,  Akira Ueno

IPC分类号： H04N23/80 ,  G11C11/413

CPC分类号： H04N23/80 ,  G11C11/413

摘要： An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.

公开(公告)号：US20210160425A1

公开(公告)日：2021-05-27

申请号：US17164961

申请日：2021-02-02

申请人： OLYMPUS CORPORATION

发明人： Yutaka Murata ,  Yoshinobu Tanaka ,  Atsushi Ishihara ,  Akira Ueno

IPC分类号： H04N5/232 ,  G11C11/413

摘要： An image processing device includes: a circuit block in which an operation period is predetermined and intermittent operation is performed according to the operation period; a plurality of SRAMs; and a dummy control circuit configured to increase an intensity of a dummy operation of an unused SRAM among the plurality of SRAMs for a certain period of time before the operation period of the circuit block, and to decrease the intensity of the dummy operation of the unused SRAM among the plurality of SRAMs for a certain period of time after the operation period of the circuit block.