公开(公告)号：US20220337029A1

公开(公告)日：2022-10-20

申请号：US17854921

申请日：2022-06-30

Applicant: Nuvoton Technology Corporation Japan

Inventor： Kouki YAMAMOTO ,  Shinichi AKIYOSHI ,  Masatoshi TANIOKU ,  Haruhisa TAKATA

IPC: H01S5/042 ,  H01L23/00 ,  H01S5/0236 ,  H01S5/02345 ,  G01S7/481

Abstract: A semiconductor device of a hybrid type includes: a light-emitting element forming a power loop; a semiconductor integrated circuit element including a switching element; and a bypass capacitor. The light-emitting element and the switching element constitute a layered body in which respective principal surfaces of the light-emitting element and the switching element are layered in parallel and face-to-face. The bypass capacitor includes one electrode connected to a lower element of the layered body, and an other electrode connected to an upper element of the layered body. In a plan view, when a direction from the one electrode to the other electrode inside the bypass capacitor is a first direction, the bypass capacitor is arranged so that a side of the bypass capacitor parallel to the first direction includes a portion that is parallel to and faces one peripheral side of the layered body.

公开(公告)号：US20230307393A1

公开(公告)日：2023-09-28

申请号：US18044746

申请日：2022-02-10

Applicant: Nuvoton Technology Corporation Japan

Inventor： Kouki YAMAMOTO ,  Shinichi AKIYOSHI ,  Ryouichi AJIMOTO

IPC: H01L23/00 ,  H01L29/78 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L24/08 ,  H01L25/0655 ,  H01L29/7813 ,  H01L2224/06152 ,  H01L2224/08225

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

公开(公告)号：US20240030167A1

公开(公告)日：2024-01-25

申请号：US18477224

申请日：2023-09-28

Applicant: Nuvoton Technology Corporation Japan

Inventor： Kouki YAMAMOTO ,  Shinichi AKIYOSHI ,  Ryouichi AJIMOTO

IPC: H01L23/00 ,  H01L25/065 ,  H01L29/78

CPC classification number: H01L24/06 ,  H01L24/08 ,  H01L25/0655 ,  H01L29/7813 ,  H01L2224/06152 ,  H01L2224/08225

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.