公开(公告)号：US11854476B1

公开(公告)日：2023-12-26

申请号：US17841696

申请日：2022-06-16

Applicant: Novatek Microelectronics Corp.

Inventor： Yao-Min Chou ,  Kai-Wen Shao

IPC: G09G3/3208 ,  G06T1/20

CPC classification number: G09G3/3208 ,  G06T1/20 ,  G09G2310/08 ,  G09G2360/02 ,  G09G2360/18

Abstract: The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal.

公开(公告)号：US20230410732A1

公开(公告)日：2023-12-21

申请号：US17841696

申请日：2022-06-16

Applicant: Novatek Microelectronics Corp.

Inventor： Yao-Min Chou ,  Kai-Wen Shao

IPC: G09G3/3208 ,  G06T1/20

CPC classification number: G09G3/3208 ,  G06T1/20 ,  G09G2310/08 ,  G09G2360/12 ,  G09G2360/18

Abstract: The disclosure is directed to a timing controller having a mechanism for frame synchronization, a display panel having the timing controller thereof, and a display system having the timing controller thereof. According to an aspect of the disclosure, the disclosure provides an integrated circuit which includes a timing controller to transmit a first TE signal to an application processor and receive a first image frame from the application processor after the application processor receives the first TE signal, and a control circuit to generate a first sync signal when the timing controller receives the first image frame, wherein when the application processor receives a second TE signal and the application processor is not ready to transmit a second image frame to the timing controller, the control circuit delays a first waiting period to generate a second sync signal.

公开(公告)号：US20230072161A1

公开(公告)日：2023-03-09

申请号：US17468647

申请日：2021-09-07

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yu-Ju Lin ,  Kai-Wen Shao ,  Yao-Min Chou

IPC: G09G3/20

Abstract: The present invention provides a method of display control for a display driver circuit operated in a video mode. The method includes steps of: driving a display panel to display a plurality of image frames having a plurality of active frames and a plurality of blanking frames, and determining whether to transmit a notification to an application processor to indicate whether the application processor needs to output image data according to whether an incoming image frame among the plurality of image frames is one of the plurality of active frames or one of the plurality of blanking frames. Wherein, the display panel is refreshed in each of the plurality of active frames, and not refreshed in each of the plurality of blanking frames.