公开(公告)号：US20140354357A1

公开(公告)日：2014-12-04

申请号：US13904879

申请日：2013-05-29

Applicant: NXP B.V.

Inventor： Rameswor Shrestha

IPC: H03H11/28 ,  H03F3/45

CPC classification number: H03H11/28 ,  H03F3/45 ,  H03F3/45071 ,  H03F2203/45441 ,  H04L25/0266 ,  H04L25/0276 ,  H04L25/0292

Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.

Abstract translation: 提供了一种装置，其包括被配置为使用多个差分信号线进行通信的第一和第二IC。 该装置包括具有多个共模电压调节电路的共模抑制电路，每个共模电压调节电路被配置为提供用于共模信号的低阻抗路径和用于差分AC信号的高阻抗路径，由此抑制 电压域。 多个共模电压调节电路各自具有阻抗匹配直到阻抗公差规范的部件。 共模抑制电路还包括AC耦合电路，其被配置为通过将来自每个差分信号线的阻抗差通过AC耦合电路交叉耦合而超过阻抗公差规范，而不依赖于阻抗失配， 共模电压调节电路。

公开(公告)号：US20160119030A1

公开(公告)日：2016-04-28

申请号：US14526128

申请日：2014-10-28

Applicant: NXP B.V.

Inventor： Rameswor Shrestha

IPC: H04B5/00

CPC classification number: H04B5/0012 ,  H04B5/005 ,  H04L25/0266

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for communicating data between capacitive-isolated devices. According to an example embodiment, an apparatus includes a transmitter circuit configured to transmit a first single-ended data signal over a first signal path. The apparatus also includes a receiver circuit. The receiver circuit includes a differential amplifier having a first input coupled to receive a second single-ended signal from a second signal path of the plurality of signal paths and includes a second input coupled to receive a reference signal from a third signal path of the plurality of signal paths. The differential amplifier outputs a third single-ended signal indicative of a voltage difference between the first and second inputs. The receiver circuit also includes a common mode suppression circuit configured to remove a common mode voltage from the first and second inputs of the differential amplifier.

Abstract translation: 本公开的方面涉及用于在电容隔离设备之间传送数据的电路，设备和方法。 根据示例实施例，一种装置包括被配置为通过第一信号路径发送第一单端数据信号的发射机电路。 该装置还包括接收器电路。 接收器电路包括差分放大器，该差分放大器具有耦合以从多个信号路径的第二信号路径接收第二单端信号的第一输入，并且包括耦合以从多个信号路径中的第三信号路径接收参考信号的第二输入 的信号路径。 差分放大器输出表示第一和第二输入之间的电压差的第三单端信号。 接收器电路还包括配置成从差分放大器的第一和第二输入端去除共模电压的共模抑制电路。

公开(公告)号：US09680528B2

公开(公告)日：2017-06-13

申请号：US14526128

申请日：2014-10-28

Applicant: NXP B.V.

Inventor： Rameswor Shrestha

IPC: H04L27/00 ,  H04B5/00 ,  H04L25/02

CPC classification number: H04B5/0012 ,  H04B5/005 ,  H04L25/0266

Abstract: Aspects of the present disclosure are directed to circuits, apparatuses and methods for communicating data between capacitive-isolated devices. According to an example embodiment, an apparatus includes a transmitter circuit configured to transmit a first single-ended data signal over a first signal path. The apparatus also includes a receiver circuit. The receiver circuit includes a differential amplifier having a first input coupled to receive a second single-ended signal from a second signal path of the plurality of signal paths and includes a second input coupled to receive a reference signal from a third signal path of the plurality of signal paths. The differential amplifier outputs a third single-ended signal indicative of a voltage difference between the first and second inputs. The receiver circuit also includes a common mode suppression circuit configured to remove a common mode voltage from the first and second inputs of the differential amplifier.

公开(公告)号：US08896377B1

公开(公告)日：2014-11-25

申请号：US13904879

申请日：2013-05-29

Applicant: NXP B.V.

Inventor： Rameswor Shrestha

IPC: H03F3/45 ,  H02M3/06 ,  H04M1/00

CPC classification number: H03H11/28 ,  H03F3/45 ,  H03F3/45071 ,  H03F2203/45441 ,  H04L25/0266 ,  H04L25/0276 ,  H04L25/0292

Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.

Abstract translation: 提供了一种装置，其包括被配置为使用多个差分信号线进行通信的第一和第二IC。 该装置包括具有多个共模电压调节电路的共模抑制电路，每个共模电压调节电路被配置为提供用于共模信号的低阻抗路径和用于差分AC信号的高阻抗路径，由此抑制 电压域。 多个共模电压调节电路各自具有阻抗匹配直到阻抗公差规范的部件。 共模抑制电路还包括AC耦合电路，其被配置为通过将来自每个差分信号线的阻抗差异通过AC耦合电路交叉耦合而超过阻抗公差规范，而不依赖于阻抗失配， 共模电压调节电路。

公开(公告)号：US10119839B2

公开(公告)日：2018-11-06

申请号：US15135533

申请日：2016-04-21

Applicant: NXP B.V.

Inventor： Rameswor Shrestha ,  Franciscus Widdershoven

IPC: G01R27/26 ,  G01D5/24 ,  G06F3/044 ,  H03K17/96

Abstract: A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

公开(公告)号：US20170023382A1

公开(公告)日：2017-01-26

申请号：US15135533

申请日：2016-04-21

Applicant: NXP B.V.

Inventor： Rameswor Shrestha ,  Franciscus Widdershoven

IPC: G01D5/24

CPC classification number: G01D5/24 ,  G01R27/2605 ,  G06F3/044 ,  H03K17/9622 ,  H03K2217/960725 ,  H03K2217/96074 ,  H03K2217/960745

Abstract: A sensor circuit and method. The circuit includes a first subcircuit that includes a first sense capacitor, a first integration capacitor, and a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T. The circuit includes a second subcircuit that includes a second sense capacitor, a second integration capacitor, and a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td. A rate of discharge of the first and second integration capacitors is at least partly determined by a capacitance of the first and second sense capacitor, respectively. At time Teval, after initiation of discharge of the first and second sense capacitors, the extent to which the first and second integration capacitors have discharged is compared. A digital signal indicating the result of the comparison is outputted.

Abstract translation: 传感器电路及方法。 电路包括第一子电路，其包括第一感测电容器，第一积分电容器和第一时钟输入端，用于在时间T接收用于启动第一积分电容器放电的第一数字时钟信号。该电路包括第二子电路，其包括 第二感测电容器，第二积分电容器和第二时钟输入端，用于接收第二数字时钟信号，以在时间T + Td启动第二积分电容器的放电。 第一和第二积分电容器的放电率至少部分地由第一和第二感测电容器的电容决定。 在Teval时刻，在第一和第二感测电容器的放电开始之后，比较第一和第二积分电容器放电的程度。 输出表示比较结果的数字信号。

公开(公告)号：US08693528B1

公开(公告)日：2014-04-08

申请号：US13690500

申请日：2012-11-30

Applicant: NXP B.V.

Inventor： Rameswor Shrestha ,  Hendrik Boezen ,  Martin Bredius

IPC: H04B1/38

CPC classification number: H04L25/0276

Abstract: In one or more embodiments, a circuit is configured to receive a differential signal from a transmitter that is isolated from the receiver circuit and that includes a common-mode suppression circuit and signal combining circuit coupled to the corresponding lines carrying the differential signals. The common-mode suppression and signal combining circuits are configured to suppress common-mode signals of differential signals communicated on the set of differential signal lines and combine to form of differential-mode components of the differential signals.

Abstract translation: 在一个或多个实施例中，电路被配置为从与接收器电路隔离的发射器接收差分信号，并且包括耦合到承载差分信号的相应线路的共模抑制电路和信号组合电路。 共模抑制和信号组合电路被配置为抑制在该组差分信号线上传送的差分信号的共模信号并且组合成差分信号的差分模式分量的形式。

公开(公告)号：US08680690B1

公开(公告)日：2014-03-25

申请号：US13708117

申请日：2012-12-07

Applicant: NXP B.V.

Inventor： Peter Steeneken ,  Rameswor Shrestha ,  Martijn Bredius

IPC: H01L23/49 ,  H01L23/66

CPC classification number: H01L24/49 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/05554 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49052 ,  H01L2224/4909 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/0274 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: In one embodiment, a device includes a first IC having a differential signal driver and a first isolation circuit configured to provide differential signals transmitted by the differential signal driver to a first pair of bond pads of the first IC. First and second bond wires are configured to provide differential signals from the first pair of bond pads to a second pair of bond pad included in a second IC. The second IC includes a second isolation circuit configured to provide differential signals from the second pair of bond pads to a differential receiver circuit of the second IC. The bond wires are specifically arranged such that a distance between the first and second bond wires varies by at least 10% as measured at two points along a length of the first bond wire.

Abstract translation: 在一个实施例中，设备包括具有差分信号驱动器的第一IC和被配置为将差分信号驱动器发送的差分信号提供给第一IC的第一对接合焊盘的第一隔离电路。 第一和第二接合线被配置为提供从第一对接合焊盘到包括在第二IC中的第二对接合焊盘的差分信号。 第二IC包括第二隔离电路，其被配置为将来自第二对接合焊盘的差分信号提供给第二IC的差分接收器电路。 接合线被特别布置成使得在沿着第一接合线的长度的两个点处测量的第一和第二接合线之间的距离变化至少10％。