公开(公告)号：US11586238B1

公开(公告)日：2023-02-21

申请号：US17644356

申请日：2021-12-15

Applicant: NXP B.V.

Inventor： Robert Matthew Mertens ,  Ateet Omer ,  Sanjay Kumar Wadhwa ,  Charles Eric Seaberg

IPC: G06F1/04 ,  H03K21/08 ,  H03M7/16 ,  H03K5/01 ,  H03K5/00

Abstract: A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.

公开(公告)号：US10892758B1

公开(公告)日：2021-01-12

申请号：US17038702

申请日：2020-09-30

Applicant: NXP B.V.

Inventor： Charles Eric Seaberg ,  Khoi Mai

IPC: H03K19/017 ,  H04L25/02 ,  H03K17/16 ,  G05F3/24

Abstract: A receiver includes an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node, a second switch coupled between the input node and a second node, a first resistive element coupled between the first node and a reference node, a second resistive element coupled between the second node and the reference node, a first capacitive element coupled to the first node, and a second capacitive element coupled to the second node. The receiver also includes a comparator having a first input coupled to the input node to receive the analog signal, and a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator controls the first and second switches.