公开(公告)号：US10979084B2

公开(公告)日：2021-04-13

申请号：US16471617

申请日：2017-01-06

Applicant: Nokia Technologies Oy

Inventor： Jingyuan Sun ,  Yi Zhang ,  Xiangnian Zeng ,  Wei Jiang ,  Dongyang Du ,  Keeth Saliya Jayasinghe

IPC: H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/27 ,  H03M13/00

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

公开(公告)号：US11196445B2

公开(公告)日：2021-12-07

申请号：US16610620

申请日：2017-05-04

Applicant: Nokia Technologies Oy ,  Alcatel Lucent

Inventor： Keeth Saliya Jayasinghe ,  Yu Chen ,  Dongyang Du ,  Jie Chen

IPC: H03M13/00 ,  H03M13/09 ,  H03M13/27 ,  H04L1/00

Abstract: A method including determining a cyclic redundancy check (CRC) generator sequence defining a one to one mapping between a sequence of control information values and cyclic redundancy check (CRC) sequence values; and determining a combined sequence, the combined sequence formed by distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values, wherein the distributing the cyclic redundancy check (CRC) value sequence within the sequence of control information values is based on a selected part of the cyclic redundancy check (CRC) generator sequence.

公开(公告)号：US11044047B2

公开(公告)日：2021-06-22

申请号：US16637789

申请日：2017-08-10

Applicant: NOKIA TECHNOLOGIES OY

Inventor： Jingyuan Sun ,  Dongyang Du ,  Wei Jiang ,  Xiangnian Zeng ,  Yi Zhang

IPC: H04L1/00 ,  H03M13/11 ,  H03M13/25

Abstract: A method comprises receiving information on a selected redundancy version at a user device. The redundancy version is associated with block coding. The block coding may be LDPC. The method may comprise using the information when communicating with a base station. The position of the redundancy version may satisfy one or more criteria.

公开(公告)号：US20200244290A1

公开(公告)日：2020-07-30

申请号：US16471617

申请日：2017-01-06

Applicant: Nokia Technologies Oy

Inventor： Jingyuan Sun ,  Yi Zhang ,  Xiangnian Zeng ,  Wei Jiang ,  Dongyang Du ,  Keeth Saliya Jayasinghe

IPC: H03M13/00 ,  H03M13/03 ,  H03M13/11 ,  H03M13/15 ,  H03M13/27

Abstract: A base matrix is applied to an LDPC coder. The base matrix includes multiple parts, each including multiple of rows and columns, and containing integers, each representative of an identity matrix cyclically shifted in accordance with the integer or representative of an all-zero matrix. At least two of the multiple parts are configured such that their respective column-wise combinations of rows represents a same starting vector, cyclically shifted or interleaved, with zero or more but not all integers not indicative of the all-zero matrix of the same vector substituted by integers indicative of the all-zero matrix. The at least two of the multiple parts are not identical. The applied base matrix is used for one of encoding data using the LDPC coder or decoding data using the LDPC coder.

公开(公告)号：US11165536B2

公开(公告)日：2021-11-02

申请号：US16494050

申请日：2017-03-15

Applicant: NOKIA TECHNOLOGIES OY

Inventor： Keeth Saliya Jayasinghe Laddu ,  Jie Chen ,  Dongyang Du ,  Yu Chen

IPC: H03M13/00 ,  H04L1/00

Abstract: A method for encoding a sequence of control information bits comprising: generating a sequence of error detection bits based on the sequence of control information bits; generating a sequence of error correction bits based on the sequence of control information bits; and distributing the sequence of error detection bits and the sequence of error correction bits between the sequence of control information bits to form a combined sequence of bits, such that the bit order of the combined sequence of bits following the distribution enables an error detection check to be performed before or after a first error correction check bit.