公开(公告)号：US11817360B2

公开(公告)日：2023-11-14

申请号：US16220160

申请日：2018-12-14

申请人： NEXPERIA B.V.

发明人： Loh Choong Keat ,  Edward Then ,  Weng Khoon Mong

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L23/13 ,  H01L21/56 ,  H01L23/544 ,  H01L23/16

CPC分类号： H01L23/3171 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3185 ,  H01L23/544 ,  H01L24/32 ,  H01L24/96 ,  H01L24/83 ,  H01L24/97 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/97 ,  H01L2924/1815 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/83862 ,  H01L2924/00014 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014

摘要： A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.