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公开(公告)号：US09729322B2
公开(公告)日：2017-08-08
申请号：US15093044
申请日：2016-04-07
Applicant: NAGRAVISION S.A.
Inventor： Roan Hautier , Marco Macchetti , Jerome Perrine
CPC classification number: H04L9/0897 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/76 , H04L9/0643 , H04L9/0869 , H04L9/0877 , H04L9/14 , H04L2209/24
Abstract: Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.
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公开(公告)号：US20150270962A1
公开(公告)日：2015-09-24
申请号：US14432426
申请日：2013-10-08
Applicant: NAGRAVISION S.A.
Inventor： Roan Hautier , Marco Macchetti , Jerome Perrine
CPC classification number: H04L9/0897 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/76 , H04L9/0643 , H04L9/0869 , H04L9/0877 , H04L9/14 , H04L2209/24
Abstract: Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.
Abstract translation: 用于个性化芯片的方法和系统，旨在集成到智能卡中，包括与连接到芯片的FPGA器件相关联的测试器，该芯片是包括多个芯片的晶片的一部分，以及用于验证存在的一次性硬件模块 的晶片上的芯片。 测试仪向FPGA设备发送第一个密码，命令芯片启动测试模式激活。 FPGA设备通过使用由从芯片接收的随机数参数化的秘密加密算法和第一密码来加密第二密码，以获得发送到芯片的第一密码。 芯片通过对使用使用随机数和第一秘密码参数化的逆算法对第一密码进行解密获得的结果执行布尔函数来确定第二密码。 将第二密码与通过临时存储在芯片上的第二密码执行布尔函数获得的结果进行比较。 仅当第二个密码符合计算结果时，FPGA器件才会对芯片进行个性化设置。
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公开(公告)号：US11206145B2
公开(公告)日：2021-12-21
申请号：US16763121
申请日：2018-11-12
Applicant: NAGRAVISION S.A.
Inventor： Sebastien Bellon , Claudio Favi , Roan Hautier , Marco Macchetti , Jerome Perrine
Abstract: An integrated circuit and a method of configuring a plurality of integrated circuits are disclosed. Each integrated circuit comprises a cryptographic key specific to it. Each integrated circuit comprises a cryptographic key specific to it. Each cryptographic key can be generated on the respective integrated circuit using a physical unclonable function and data associated with the cryptographic key, e.g. a configuration message comprising instructions for generating the cryptographic key using the physical unclonable function. The cryptographic key specific to the integrated circuit is not stored on the integrated circuit. Each of the plurality of integrated circuits are configured using a data file that is encrypted with the respective cryptographic key specific to the integrated circuit, circuit.
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公开(公告)号：US09338004B2
公开(公告)日：2016-05-10
申请号：US14432426
申请日：2013-10-08
Applicant: NAGRAVISION S.A.
Inventor： Roan Hautier , Marco Macchetti , Jerome Perrine
CPC classification number: H04L9/0897 , G06F21/31 , G06F21/44 , G06F21/572 , G06F21/76 , H04L9/0643 , H04L9/0869 , H04L9/0877 , H04L9/14 , H04L2209/24
Abstract: Method and system for personalizing a chip, intended to be integrated into a smart card, comprising a tester associated to an FPGA device connected to the chip, the chip being part of a wafer comprising a plurality of chips and a disposable hardware module for verifying presence of the chip on the wafer. The tester sends a first secret code to the FPGA device, which commands the chip to initiate a test mode activation. The FPGA device encrypts a second secret code by using a secret encryption algorithm parameterized with a random number received from the chip and the first secret code to obtain a first cryptogram which is sent to the chip. The chip determines a second cryptogram by carrying out a Boolean function over a result obtained by decryption of the first cryptogram using the inverse algorithm parameterized with the random number and the first secret code. The second cryptogram is compared with a result obtained by carrying out the Boolean function over the second secret code temporarily stored on the chip. The FPGA device personalizes the chip only if the second cryptogram matches the calculated result.
Abstract translation: 用于个性化芯片的方法和系统，旨在集成到智能卡中，包括与连接到芯片的FPGA器件相关联的测试器，该芯片是包括多个芯片的晶片的一部分，以及用于验证存在的一次性硬件模块 的晶片上的芯片。 测试仪向FPGA设备发送第一个密码，命令芯片启动测试模式激活。 FPGA设备通过使用由从芯片接收的随机数参数化的秘密加密算法和第一密码来加密第二密码，以获得发送到芯片的第一密码。 芯片通过对使用使用随机数和第一秘密码参数化的逆算法对第一密码进行解密获得的结果执行布尔函数来确定第二密码。 将第二密码与通过临时存储在芯片上的第二密码执行布尔函数获得的结果进行比较。 仅当第二个密码符合计算结果时，FPGA器件才会对芯片进行个性化设置。
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