公开(公告)号：US20240303217A1

公开(公告)日：2024-09-12

申请号：US18661457

申请日：2024-05-10

申请人： Mythic, Inc.

发明人： David Fick ,  Malav Parikh ,  Paul Toth ,  Adam Caughron ,  Vimal Reddy ,  Erik Schlanger ,  Sergio Schuler ,  Zainab Nasreen Zaidi ,  Alex Dang-Tran ,  Raul Garibay ,  Bryant Sorensen

IPC分类号： G06F15/78 ,  G06F9/38 ,  G06F15/173 ,  G06F17/16 ,  H04L45/00

CPC分类号： G06F15/7825 ,  G06F9/3887 ,  G06F15/173 ,  G06F15/17337 ,  G06F15/7814 ,  G06F17/16 ,  H04L45/34 ,  H04L45/38

摘要： A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

公开(公告)号：US11360932B2

公开(公告)日：2022-06-14

申请号：US16790240

申请日：2020-02-13

申请人： Mythic, Inc.

发明人： David Fick ,  Malav Parikh ,  Paul Toth ,  Adam Caughron ,  Vimal Reddy ,  Erik Schlanger ,  Sergio Schuler ,  Zainab Nasreen Zaidi ,  Alex Dang-Tran ,  Raul Garibay ,  Bryant Sorensen

IPC分类号： G06F15/78 ,  G06F15/173 ,  G06F17/16 ,  H04L45/00 ,  G06F9/38

摘要： A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

公开(公告)号：US11475973B2

公开(公告)日：2022-10-18

申请号：US17331095

申请日：2021-05-26

申请人： Mythic, Inc.

发明人： Malav Parikh ,  Zainab Nasreen Zaidi ,  Sergio Schuler ,  Natarajan Seshan ,  Raul A. Garibay, Jr. ,  David Fick

IPC分类号： G11C29/44 ,  G06F12/1009 ,  G11C29/38

摘要： A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.

公开(公告)号：US20220276983A1

公开(公告)日：2022-09-01

申请号：US17745742

申请日：2022-05-16

申请人： Mythic, Inc.

发明人： David Fick ,  Malav Parikh ,  Paul Toth ,  Adam Caughron ,  Vimal Reddy ,  Erik Schlanger ,  Sergio Schuler ,  Zainab Nasreen Zaidi ,  Alex Dang-Tran ,  Raul Garibay ,  Bryant Sorensen

IPC分类号： G06F15/78 ,  G06F15/173 ,  G06F17/16 ,  H04L45/00 ,  G06F9/38

摘要： A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.

公开(公告)号：US11016810B1

公开(公告)日：2021-05-25

申请号：US17102643

申请日：2020-11-24

申请人： Mythic, Inc.

发明人： Malav Parikh ,  Sergio Schuler ,  Vimal Reddy ,  Zainab Zaidi ,  Paul Toth ,  Adam Caughron ,  Bryant Sorensen ,  Alex Dang-Tran ,  Scott Johnson ,  Raul Garibay ,  Andrew Morten ,  David Fick

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F7/57 ,  G06F15/76 ,  G06F9/302 ,  G06N3/04 ,  G06F7/544 ,  G06F15/78 ,  G06F9/30

摘要： A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

公开(公告)号：US20200012617A1

公开(公告)日：2020-01-09

申请号：US16458917

申请日：2019-07-01

申请人： Mythic, Inc.

发明人： David Fick ,  Malav Parikh ,  Paul Toth ,  Adam Caughron ,  Vimal Reddy ,  Erik Schlanger ,  Sergio Schuler ,  Zainab Nasreen Zaidi ,  Alex Dang-Tran ,  Raul Garibay ,  Bryant Sorensen

IPC分类号： G06F15/78 ,  G06F15/173 ,  G06F17/16 ,  H04L12/721 ,  G06F9/38

摘要： Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.

公开(公告)号：US10521395B1

公开(公告)日：2019-12-31

申请号：US16458917

申请日：2019-07-01

申请人： Mythic, Inc.

发明人： David Fick ,  Malav Parikh ,  Paul Toth ,  Adam Caughron ,  Vimal Reddy ,  Erik Schlanger ,  Sergio Schuler ,  Zainab Nasreen Zaidi ,  Alex Dang-Tran ,  Raul Garibay ,  Bryant Sorensen

IPC分类号： G06F15/78 ,  G06F15/173 ,  G06F9/38 ,  H04L12/721 ,  G06F17/16

摘要： Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.

公开(公告)号：US20240311194A1

公开(公告)日：2024-09-19

申请号：US18672842

申请日：2024-05-23

申请人： Mythic, Inc.

发明人： Malav Parikh ,  Sergio Schuler ,  Vimal Reddy ,  Zainab Zaidi ,  Paul Toth ,  Adam Caughron ,  Bryant Sorensen ,  Alex Dang-Tran ,  Scott Johnson ,  Raul Garibay ,  Andrew Morten ,  David Fick

IPC分类号： G06F9/50 ,  G06F7/544 ,  G06F7/57 ,  G06F9/30 ,  G06F9/48 ,  G06F15/78 ,  G06N3/045

CPC分类号： G06F9/5027 ,  G06F9/4843 ,  G06N3/045 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/5061 ,  G06F15/7807

摘要： A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

公开(公告)号：US20210280266A1

公开(公告)日：2021-09-09

申请号：US17331095

申请日：2021-05-26

申请人： Mythic, Inc.

发明人： Malav Parikh ,  Zainab Nasreen Zaidi ,  Sergio Schuler ,  Natarajan Seshan ,  Raul A. Garibay, Jr. ,  David Fick

IPC分类号： G11C29/44 ,  G06F12/1009 ,  G11C29/38

摘要： A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.

公开(公告)号：US20210232435A1

公开(公告)日：2021-07-29

申请号：US17231089

申请日：2021-04-15

申请人： Mythic, Inc.

发明人： Malav Parikh ,  Sergio Schuler ,  Vimal Reddy ,  Zainab Zaidi ,  Paul Toth ,  Adam Caughron ,  Bryant Sorensen ,  Alex Dang-Tran ,  Scott Johnson ,  Raul Garibay ,  Andrew Morten ,  David Fick

IPC分类号： G06F9/50 ,  G06N3/04 ,  G06F9/48

摘要： A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.