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公开(公告)号：US12124391B2
公开(公告)日：2024-10-22
申请号：US18218426
申请日：2023-07-05
发明人： Stephen Sangho Youn , Steven Karl Reinhardt , Jeremy Halden Fowers , Lok Chand Koppaka , Kalin Ovtcharov
CPC分类号： G06F13/4027 , G06N3/04
摘要： The present disclosure relates to devices for using a configurable stacked architecture for a fixed function datapath with an accelerator for accelerating an operation or a layer of a deep neural network (DNN). The stacked architecture may have a fixed function datapath that includes one or more configurable micro-execution units that execute a series of vector, scalar, reduction, broadcasting, and normalization operations for a DNN layer operation. The fixed function datapath may be customizable based on the DNN or the operation.
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公开(公告)号：US11734214B2
公开(公告)日：2023-08-22
申请号：US17212751
申请日：2021-03-25
发明人： Stephen Sangho Youn , Steven Karl Reinhardt , Jeremy Halden Fowers , Lok Chand Koppaka , Kalin Ovtcharov
CPC分类号： G06F13/4027 , G06N3/04
摘要： The present disclosure relates to devices for using a configurable stacked architecture for a fixed function datapath with an accelerator for accelerating an operation or a layer of a deep neural network (DNN). The stacked architecture may have a fixed function datapath that includes one or more configurable micro-execution units that execute a series of vector, scalar, reduction, broadcasting, and normalization operations for a DNN layer operation. The fixed function datapath may be customizable based on the DNN or the operation.
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公开(公告)号：US12079137B2
公开(公告)日：2024-09-03
申请号：US18203527
申请日：2023-05-30
IPC分类号： G06F12/0897 , G11C7/10 , G11C11/4076
CPC分类号： G06F12/0897 , G11C7/1006 , G11C7/1057 , G11C7/1072 , G11C11/4076
摘要： The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.
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公开(公告)号：US12073310B2
公开(公告)日：2024-08-27
申请号：US16837171
申请日：2020-04-01
CPC分类号： G06N3/063 , G06F9/3836 , G06F9/3887 , G06F9/4843 , G06F9/5027 , G06F17/16
摘要： Deep neural network accelerators (DNNs) with independent datapaths for simultaneous processing of different classes of operations and related methods are described. An example DNN accelerator includes an instruction dispatcher for receiving chains of instructions having both instructions for performing a first class of operations and a second class of operations corresponding to a neural network model. The DNN accelerator further includes a first datapath and a second datapath, where each is configured to execute at least one instruction chain locally before outputting any results. The instruction dispatcher is configured to forward instructions for performing the first class of operations to the first datapath and forward instructions for performing the second class of operations to the second datapath to overlap in time a performance of at least a subset of the first class of operations with a performance of at least a subset of the second class of operations.
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公开(公告)号：US11704251B2
公开(公告)日：2023-07-18
申请号：US17730707
申请日：2022-04-27
IPC分类号： G06F12/08 , G06F12/00 , G11C7/10 , G06F12/0897 , G11C11/4076
CPC分类号： G06F12/0897 , G11C7/1006 , G11C7/1057 , G11C7/1072 , G11C11/4076
摘要： The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.
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公开(公告)号：US11347652B2
公开(公告)日：2022-05-31
申请号：US17097205
申请日：2020-11-13
IPC分类号： G06F12/08 , G06F12/00 , G11C7/10 , G06F12/0897 , G11C11/4076
摘要： The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.
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