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1.发明授权Memory controller and integrated circuit device for correcting errors in data read from memory cells 有权用于校正从存储器单元读取的数据中的错误的存储器控制器和集成电路器件公开(公告)号：US09448881B1
公开(公告)日：2016-09-20
申请号：US14747952
申请日：2015-06-23
CPC分类号： G06F11/1068 , G06F11/1008 , G11C29/52 , H03M13/11 , H03M13/1108 , H03M13/1111 , H03M13/116 , H03M13/2957 , H03M13/3715 , H03M13/45
摘要： An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.
摘要翻译： 用于校正从存储单元读取的数据中的错误的集成电路装置包括解码器，编码器和数据管理模块。 数据管理模块被配置为通过改变编码器使用的码率来从多个原始比特误码率限制中选择可校正的原始比特误码率限制，其中发生解码器和编码器的虚拟改变以改变码 率。
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2.发明授权公开(公告)号：US09454414B2
公开(公告)日：2016-09-27
申请号：US14210971
申请日：2014-03-14
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
CPC分类号： G06F11/00 , G06F11/1048 , H03M13/1111 , H03M13/3769
摘要： A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding.
摘要翻译： 读取，累加和处理用于LDPC解码的软信息的系统和方法。 根据本发明，LDPC解码器包括用于接收非易失性存储器存储模块的单元的软读取的积累电路，并且产生可用于识别该单元的适当LLR的累积软读。 本发明的累积电路可以包括累加RAM，算术逻辑单元（ALU）和用于累积和处理用于LDPC解码的软信息的软累积控制和排序模块。
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公开(公告)号：US09397701B1
公开(公告)日：2016-07-19
申请号：US13792831
申请日：2013-03-11
CPC分类号： H03M13/13 , G06F11/1012 , G11C2211/5634 , H03M13/1111 , H03M13/3723 , H03M13/612
摘要： A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of the memory storage module, wherein each of the plurality of lifetime specific LLR look-up tables comprises a plurality of LLRs representative of a specific point in the lifetime of the memory storage module for each of the plurality of soft-decision bits. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 提供了一种非易失性存储器存储控制器，用于将对数似然比（LLR）传送到用于LDPC编码码字的解码中的低密度奇偶校验（LDPC）解码器。 控制器包括用于使用多个软判决参考电压读取存储在非易失性存储器存储模块中的LDPC编码码字的读取电路，以提供表示代码字的多个软判决位。 控制器还包括表示存储器存储模块的寿命阈值电压分布的多个寿命特定的LLR查找表，其中多个寿命特定的LLR查找表中的每一个包括表示特定点的多个LLR 在多个软判决位中的每一个的存储器存储模块的寿命期内。 控制器将来自适当的LLR查找表的LLR提供给用于码字的后续解码的LDPC解码器。
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4.发明授权System and method for higher quality log likelihood ratios in LDPC decoding 有权LDPC解码中较高质量对数似然比的系统和方法公开(公告)号：US09590656B2
公开(公告)日：2017-03-07
申请号：US14210067
申请日：2014-03-13
发明人： Rino Micheloni , Alessia Marelli , Peter Z. Onufryk , Christopher I. W. Norrie , Ihab Jaser , Luca Crippa
IPC分类号： H03M13/00 , H03M13/11 , H03M13/39 , H03M13/25 , H04L1/00 , H03M13/15 , G06F11/10 , H03M13/37
CPC分类号： H03M13/1111 , G06F11/10 , G06F11/1012 , H03M13/15 , H03M13/255 , H03M13/3723 , H03M13/3927 , H04L1/0057
摘要： A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword.
摘要翻译： 提供了一种非易失性存储器存储控制器，用于将对数似然比（LLR）传送到用于LDPC编码码字的解码中的低密度奇偶校验（LDPC）解码器。 控制器包括用于使用多个软判决参考电压读取存储在非易失性存储器存储模块中的LDPC编码码字的读取电路，以提供表示代码字的多个软判决位。 控制器还包括表示相邻小区对存储器存储模块的阈值电压分布的贡献的多个相邻小区贡献LLR查找表。 控制器将来自适当的LLR查找表的LLR提供给用于码字的后续解码的LDPC解码器。
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