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    MEMORY DEVICE WITH A MULTI-MODE COMMUNICATION MECHANISM
    1.
    发明申请
    MEMORY DEVICE WITH A MULTI-MODE COMMUNICATION MECHANISM 审中-公开

    公开(公告)号：US20190373076A1

    公开(公告)日：2019-12-05

    申请号：US16540568

    申请日：2019-08-14

    申请人： Micron Technology, Inc.

    发明人： Matthew D. Rowley ,  Mark Bauer

    IPC分类号： H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16

    摘要： A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

    Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
    2.
    发明授权
    Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array 有权
    用于多级单元存储器的数据路径，存储方法和利用存储器阵列的方法

    公开(公告)号：US08787081B2

    公开(公告)日：2014-07-22

    申请号：US13938022

    申请日：2013-07-09

    申请人： Micron Technology, Inc.

    发明人： Mark Bauer

    IPC分类号： G11C11/34 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C2211/5641

    摘要： Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.

    摘要翻译： 公开了存储器，数据路径，存储方法和利用方法，包括使用多级存储单元的存储器的数据路径，以提供每存储器单元多位的存储。 一个这样的数据路径包括位映射电路和数据转换器电路。 这样的位映射电路可以被配置为将原始数据的位映射到位的中间排列，并且这样的数据转换器电路可以被配置为接收位的中间排列，并将位的中间排列转换成对应于 由存储单元阵列的存储单元存储的存储器状态。

    Memory device with a multi-mode communication mechanism
    3.
    发明授权
    Memory device with a multi-mode communication mechanism 有权

    公开(公告)号：US10419574B2

    公开(公告)日：2019-09-17

    申请号：US15684831

    申请日：2017-08-23

    申请人： Micron Technology, Inc.

    发明人： Matthew D. Rowley ,  Mark Bauer

    IPC分类号： G11C8/00 ,  H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16

    摘要： A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

    MEMORY DEVICE WITH A MULTI-MODE COMMUNICATION MECHANISM
    4.
    发明申请
    MEMORY DEVICE WITH A MULTI-MODE COMMUNICATION MECHANISM 审中-公开

    公开(公告)号：US20190068743A1

    公开(公告)日：2019-02-28

    申请号：US15684831

    申请日：2017-08-23

    申请人： Micron Technology, Inc.

    发明人： Matthew D. Rowley ,  Mark Bauer

    IPC分类号： H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16

    CPC分类号： H04L67/2885 ,  G06F13/1668 ,  H04L67/2838 ,  H04L69/18 ,  H04W88/06 ,  H04W88/16

    摘要： A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

    Memory device with a multi-mode communication mechanism
    9.
    发明授权
    Memory device with a multi-mode communication mechanism 有权

    公开(公告)号：US10805422B2

    公开(公告)日：2020-10-13

    申请号：US16540568

    申请日：2019-08-14

    申请人： Micron Technology, Inc.

    发明人： Matthew D. Rowley ,  Mark Bauer

    IPC分类号： G06F12/02 ,  H04L29/08 ,  H04W88/06 ,  H04L29/06 ,  H04W88/16 ,  G06F13/16

    摘要： A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

    DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY
    10.
    发明申请
    DATA PATH FOR MULTI-LEVEL CELL MEMORY, METHODS FOR STORING AND METHODS FOR UTILIZING A MEMORY ARRAY 有权
    用于多级细胞存储器的数据路径，用于存储的方法和使用存储器阵列的方法

    公开(公告)号：US20130294159A1

    公开(公告)日：2013-11-07

    申请号：US13938022

    申请日：2013-07-09

    申请人： Micron Technology, Inc.

    发明人： Mark Bauer

    IPC分类号： G11C16/06

    CPC分类号： G11C16/10 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/06 ,  G11C2211/5641

    摘要： Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.

    摘要翻译： 公开了存储器，数据路径，存储方法和利用方法，包括使用多级存储单元的存储器的数据路径，以提供每存储器单元多位的存储。 一个这样的数据路径包括位映射电路和数据转换器电路。 这样的位映射电路可以被配置为将原始数据的位映射到位的中间排列，并且这样的数据转换器电路可以被配置为接收位的中间排列，并将位的中间排列转换成对应于 由存储单元阵列的存储单元存储的存储器状态。