公开(公告)号：US12081427B2

公开(公告)日：2024-09-03

申请号：US17191736

申请日：2021-03-04

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Arnon Sattinger ,  Dotan David Levi ,  Avraham Ganor ,  Shahar Givony ,  Nimer Khazen

IPC: H04L43/50 ,  H04L43/08 ,  H04L43/10

CPC classification number: H04L43/50 ,  H04L43/08 ,  H04L43/10

Abstract: A pluggable module, for testing time-synchronization signals of network elements, includes a first connector for connecting to test equipment, a second connector for connecting to a network port of a network element, and at least one driver. The at least one driver is connected between the first and second connectors and is configured to buffer and relay a time-synchronization signal between the network element and the test equipment.

公开(公告)号：US20240248455A1

公开(公告)日：2024-07-25

申请号：US18100296

申请日：2023-01-23

Applicant: Mellanox Technologies, Ltd.

Inventor： Tahir Cader ,  Siddha Ganju ,  Avraham Ganor ,  Ran Hasson Ruso ,  Elad Mentovich

IPC: G05B19/4155

CPC classification number: G05B19/4155 ,  G05B2219/49216

Abstract: Methods, apparatuses, and computer program products for proactive thermal management and processing core selection are provided. An example method includes receiving a job packet that is associated with a packet profile and determining one or more performance parameters associated with a performance of the job packet as defined by the packet profile. The method further includes generating a proactive thermal management procedure based upon the one or more performance parameters and associating the proactive thermal management procedure with the job packet. The method may further include determining a selected processing core from amongst a plurality of processing cores for the performance of the job packet based upon one or more operating characteristics of the processing cores and/or one or more performance parameters of the job packet.

公开(公告)号：US20240080229A1

公开(公告)日：2024-03-07

申请号：US17948717

申请日：2022-09-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Elad Mentovich ,  Avraham Ganor ,  Juan Jose Vegas Olmos ,  Ioannis (Giannis) Patronas ,  Paraskevas Bakopoulos

IPC: H04L25/03

CPC classification number: H04L25/03038 ,  H04L2025/03815

Abstract: Systems, methods, apparatuses, and computer program products for reducing data port downtime are provided. An example network interface device of the present disclosure includes a first data port and a second data port. The network interface device performs a first link training process associated with the first data port coupled to a first communication link to determine a first communication parameter set for the first communication link. The network interface device then deactivates the first data port and performs a second link training process associated the second data port coupled to a second communication link to determine a second communication parameter set. Based on a network usage parameter set associated with a data plane of the network interface device, the network interface device determines whether to activate the first data port concurrently with the second data port.

公开(公告)号：US20220269639A1

公开(公告)日：2022-08-25

申请号：US17183552

申请日：2021-02-24

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Avraham Ganor

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

Abstract: Systems and method are provided. An illustrative system includes a first compute node having a first processing unit, a first compute node port, and a first peripheral component interconnect bus configured to carry data between the first processing unit and the first compute node port. The system may further include a multi-host network interface controller having a first multi-host port, where the first multi-host port is configured to connect with the first compute node port via a first peripheral component interconnect cable, a network port, where the network port is configured to receive a network interface of a networking cable, and processing circuitry configured to translate and carry data between the first multi-host port and the network port.

公开(公告)号：US10831694B1

公开(公告)日：2020-11-10

申请号：US16446632

申请日：2019-06-20

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avraham Ganor ,  Ashrut Ambastha ,  Yael Shenhav ,  Samuel Attali

IPC: G06F13/42

Abstract: In one embodiment, an external multi-host system includes an external peripheral component bus (PCB) cable terminated with a first and second PCB connector plug, a first network host including a first processor and a first PCB connector receptacle to receive the first PCB connector plug, and a second network host including a second processor and a multi-host network interface card, which includes a network connector receptacle to receive a first network connector plug terminating a network cable, a second PCB connector receptacle to provide connectivity with the first network host and to receive the second PCB connector plug, a first PCB edge-connector to provide connectivity with the second processor, and processing circuitry to operate communication with the first network host over the external PCB cable and with the second processor via the first PCB edge-connector, and exchange network packets between the network hosts and a network.

公开(公告)号：US10657077B2

公开(公告)日：2020-05-19

申请号：US16104958

申请日：2018-08-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Avraham Ganor ,  Reuven Badash

IPC: G06F3/00 ,  G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.

公开(公告)号：US12176945B2

公开(公告)日：2024-12-24

申请号：US17869997

申请日：2022-07-21

Applicant: Mellanox Technologies, Ltd.

Inventor： Paraskevas Bakopoulos ,  Ioannis (Giannis) Patronas ,  Nikolaos Argyris ,  Dimitrios Syrivelis ,  Elad Mentovich ,  Dimitrios Kalavrouziotis ,  Avraham Ganor ,  Nimer Hazin

IPC: H04B10/00 ,  H04B10/038 ,  H04B10/112 ,  H04B10/40

Abstract: A transceiver module for providing operational resilience is presented. The transceiver module is configured to receive first data via a first optical module in a first configuration of operation and detect, using an adapter that is operationally connected to the first optical module, an operational failure of the first optical module. In response to detecting the operational failure, the transceiver module is configured to switch, via the adapter, from the first configuration of operation to a second configuration of operation by: automatically engaging a second optical module; triggering the first data that was initially directed into a first input port of the first optical module to be directed into a second input port of the second optical module; and receiving the first data from a second output port of the second optical module.

公开(公告)号：US11070304B1

公开(公告)日：2021-07-20

申请号：US16799873

申请日：2020-02-25

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Liron Mula ,  Avraham Ganor ,  Avi Urman ,  Aviad Raveh ,  Yuval Itkin ,  Oren Matus

IPC: H04J3/06

Abstract: In one embodiment, a computer apparatus includes a first NIC including at least one network interface port to transfer data with a first packet-data network (PDN) including a master clock to provide a clock synchronization signal S1, a first physical hardware clock (PHC) to maintain a time value T1 responsively to S1, and a first clock controller to generate a clock synchronization signal S2 responsively to S1, S2 having a frequency set responsively to S1, and send S2 over a connection to a second NIC including at least one network interface port to transfer data with a second PDN, a second PHC, and a second clock controller to receive S2, update the second PHC with a time value T2 responsively to S2, send another clock synchronization signal to network nodes in the second PDN responsively to T2, the second NIC acting as a master clock in the second PDN.

公开(公告)号：US11003607B2

公开(公告)日：2021-05-11

申请号：US16846341

申请日：2020-04-12

Applicant: Mellanox Technologies, Ltd.

Inventor： Avraham Ganor ,  Reuven Badash

IPC: G06F13/36 ,  G06F3/06 ,  G06F3/00 ,  G06F13/00 ,  G06F13/38 ,  G06F13/40

Abstract: A storage and communication apparatus for plugging into a server, includes a circuit board, a bus interface, a Medium Access Control (MAC) processor, one or more storage devices and at least one Central Processing Unit (CPU). The bus interface is configured to connect the apparatus at least to a processor of the server. The MAC is mounted on the circuit board and is configured to connect to a communication network. The storage devices are mounted on the circuit board and are configured to store data. The CPU is mounted on the circuit board and is configured to expose the storage devices both (i) to the processor of the server via the bus interface, and (ii) indirectly to other servers over the communication network.

公开(公告)号：US10010007B2

公开(公告)日：2018-06-26

申请号：US14963266

申请日：2015-12-09

Applicant: Mellanox Technologies Ltd.

Inventor： Yuval Itkin ,  Avraham Ganor ,  Andrey Blyahman

IPC: H05K1/11 ,  H05K7/14 ,  H05K3/46 ,  G06F1/18 ,  H01R13/66 ,  H01R13/187 ,  H05K1/02 ,  H05K1/14

CPC classification number: H05K7/1452 ,  G06F1/185 ,  H05K1/028 ,  H05K1/117 ,  H05K1/148 ,  H05K3/4611 ,  H05K3/4691 ,  H05K7/1439 ,  H05K2201/10189

Abstract: Electronic apparatus includes a laminated multi-layer circuit substrate, including first and second rigid cards and a flexible section between the first and second rigid cards. First and second sets of electrical terminals are disposed respectively on the first and second rigid cards and arranged to mate with respective bus connectors configured in accordance with a predefined bus standard. At least one bus interface circuit is configured to communicate over a bus in accordance with the predefined bus standard and disposed on the first rigid card. Printed conductors run continuously from the first rigid card, over the flexible section of the substrate, to the second rigid card and connect the at least one bus interface circuit on the first rigid card to the second set of electrical terminals on the second rigid card.