公开(公告)号：US06384638B1

公开(公告)日：2002-05-07

申请号：US09217668

申请日：1998-12-21

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： H03K522

CPC分类号： H03L7/0896

摘要： A differential charge pump for providing a low charge pump current. The present invention operates in one embodiment as part of an integrated circuit of a semiconductor chip by providing very small magnitude currents to other on-chip circuitry. Specifically, one embodiment of the present invention utilizes an R-2R resistor ladder circuit having moderate sized resistors to progressively reduce a large magnitude current into a very small magnitude current of accurate size. In this manner, available on-chip circuitry voltage can be used to produce the desired small magnitude of current without utilizing excessively large resistors, which can occupy too much die area. This is advantageous when dealing with specific types of on-chip components and circuitry which require accurate currents having very small magnitudes. For example, it may be desirable to integrate filter components (e.g., capacitors) on-chip together with accompanying phase lock loop (PLL) circuitry. However, smaller sized filter components typically need to be supplied accurate charge pump currents having very small magnitudes in order to produce the desired operational bandwidth. As such, the present invention is able to provide accurate charge pump currents having very small magnitudes for the smaller sized filter components from the available on-chip circuitry voltages. The present invention finds particular application within a clock generator circuit where it reduces clock jitter by enabling PLL filter components to be completely integrated on-chip.

摘要翻译： 用于提供低电荷泵电流的差动电荷泵。 本发明在一个实施例中作为半导体芯片的集成电路的一部分，通过向其他片上电路提供非常小的幅度电流来操作。 具体地说，本发明的一个实施例利用具有中等尺寸电阻器的R-2R电阻梯形电路逐渐将大幅度电流减小到精确尺寸的非常小的电流。 以这种方式，可以使用可用的片上电路电压来产生所需的小电流电流，而不会使用可能占据太多管芯面积的过大的电阻器。 当处理需要具有非常小幅度的精确电流的特定类型的片上组件和电路时，这是有利的。 例如，可能期望将片上的滤波器组件（例如，电容器）与伴随的锁相环（PLL）电路集成。 然而，较小尺寸的滤波器组件通常需要提供具有非常小幅度的精确电荷泵电流，以便产生期望的操作带宽。 因此，本发明能够从可用的片上电路电压为较小尺寸的滤波器组件提供具有非常小幅度的精确电荷泵电流。 本发明在时钟发生器电路中发现特定的应用，其中通过使PLL滤波器组件完全集成在芯片上来减少时钟抖动。

公开(公告)号：US6100726A

公开(公告)日：2000-08-08

申请号：US219200

申请日：1998-12-21

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： G05F3/22 ,  H03L7/089 ,  H03B1/00 ,  H03K3/00

CPC分类号： H03L7/0895 ,  H03L7/0896 ,  G05F3/222

摘要： A buffer circuit having a high input impedance. The buffer circuit comprises an input lead, a first stage having a first emitter follower transistor and a first level shifter transistor, a second stage having a second emitter follower transistor and a second level shifter transistor, and an output lead coupled to said second stage. The first emitter follower transistor is coupled to the input lead and coupled to the first level shifter transistor. The first and second stage of the buffer circuit acts as a voltage follower. The second emitter follower transistor is coupled to the second level shifter transistor, while the second emitter follower transistor is coupled to the first emitter follower transistor. The buffer circuit has a high input impedance and very low leakage current. Hence, it is ideal for sampling filter components of a phase lock loop circuit within a high frequency clock generation circuit thereby reducing clock jitter.

摘要翻译： 具有高输入阻抗的缓冲电路。 缓冲电路包括输入引线，第一级具有第一射极跟随器晶体管和第一电平移位晶体管，第二级具有第二射极跟随器晶体管和第二电平移位晶体管，以及耦合到所述第二级的输出引线。 第一射极跟随器晶体管耦合到输入引线并耦合到第一电平移位晶体管。 缓冲电路的第一和第二级充当电压跟随器。 第二射极跟随器晶体管耦合到第二电平移位器晶体管，而第二射极跟随器晶体管耦合到第一射极跟随器晶体管。 缓冲电路具有高输入阻抗和非常低的漏电流。 因此，理想的是在高频时钟生成电路内采样锁相环电路的滤波器组件，从而减少时钟抖动。

公开(公告)号：US06424191B1

公开(公告)日：2002-07-23

申请号：US09656303

申请日：2000-09-06

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： H03L706

CPC分类号： H03L7/0896 ,  G05F3/222 ,  H03L7/0895

摘要： A low side, low voltage current sink circuit having improved output impedance to reduce effects of leakage current. A current sink circuit is described having a transistor having its emitter coupled to an emitter degeneration resistor which is coupled to the low side (e.g., ground) of a power supply. The output of the current sink is taken at the collector of the transistor. In one embodiment, the transistor is an NPN transistor device. The base of the transistor is coupled to the output of an operational amplifier. One input of the operational amplifier is coupled in a feedback loop to the emitter of the transistor. A direct current bias voltage is applied to the other input of the operational amplifier. In this arrangement, the output impedance (R″o) of the current is sink is based on the open loop gain of the operational amplifier (e.g., about 35 dB) and is therefore orders of magnitude larger than the output impedance of other prior art current sink designs. The novel design limits the voltage drop over the emitter degeneration resistor thereby increasing the differential voltage swing at the collector of the transistor for low power applications. The present invention finds particular application within a clock generator circuit where its reduced leakage current properties and improved dynamic range help to reduce clock jitter in the clock generation circuit.

摘要翻译： 一种具有改善的输出阻抗以降低泄漏电流的影响的低侧，低压电流吸收电路。 描述了一种电流吸收电路，其具有耦合到电源的低侧（例如，接地）的发射极退化电阻的发射极的晶体管。 电流吸收器的输出在晶体管的集电极处获取。 在一个实施例中，晶体管是NPN晶体管器件。 晶体管的基极耦合到运算放大器的输出端。 运算放大器的一个输入端以反馈回路耦合到晶体管的发射极。 直流偏置电压施加到运算放大器的另一个输入端。 在这种布置中，电流的输出阻抗（R''o）是基于运算放大器的开环增益（例如，大约35dB），并且因此比其它先前的输出阻抗大一个数量级 艺术潮流设计。 新颖的设计限制了发射极退化电阻上的电压降，从而增加了用于低功率应用的晶体管集电极上的差分电压摆幅。 本发明在时钟发生器电路中具有特别的应用，其中其减小的漏电流特性和改善的动态范围有助于减少时钟产生电路中的时钟抖动。

公开(公告)号：US06304132B1

公开(公告)日：2001-10-16

申请号：US09183321

申请日：1998-10-30

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： G05F110

CPC分类号： H03L7/0896 ,  G05F3/222 ,  H03L7/0895

摘要： A high side low voltage current source circuit having improved output impedance to reduce effects of leakage current. A current source circuit is described with a transistor having an emitter coupled to an emitter degeneration resistor which is coupled to a power supply voltage. The output of the current source is taken at the collector of the transistor. In one embodiment, the transistor is a PNP transistor device. The base of the transistor is coupled to the output of an operational amplifier. One input of the operational amplifier is coupled in a feedback loop to the emitter of the transistor. A direct current bias voltage is applied to the other input of the operational amplifier. The output impedance (R″o) of the current is source is based on the open loop gain of the operational amplifier (e.g., about 35 dB) and is therefore orders of magnitude larger than the output impedance of other prior art current source designs. Also included is a novel level shifting circuit for shifting (up) the DC voltage level at the emitter of the transistor to improve its dynamic range of operation in low power supply voltage environments. A resistor is also placed in a tail current path of the operational amplifier, rather than a transistor, to further improve the dynamic range of the current source. The present invention finds particular application within a clock generator circuit where its reduced leakage current properties and improved dynamic range help to reduce clock jitter.

摘要翻译： 具有改善的输出阻抗以减少漏电流的影响的高端低压电流源电路。 电流源电路用具有耦合到发射极退化电阻器的发射极的晶体管描述，发射极退化电阻器耦合到电源电压。 电流源的输出在晶体管的集电极处获取。 在一个实施例中，晶体管是PNP晶体管器件。 晶体管的基极耦合到运算放大器的输出端。 运算放大器的一个输入端以反馈回路耦合到晶体管的发射极。 直流偏置电压施加到运算放大器的另一个输入端。 电流的输出阻抗（R'o）来源于运算放大器的开环增益（例如约35 dB），因此其数量级大于其他现有技术电流源设计的输出阻抗 。 还包括一个新颖的电平移位电路，用于移位（上升）晶体管发射极处的直流电压电平，以改善其在低电源电压环境下的动态动态范围。 电阻器也放置在运算放大器的尾电流路径中，而不是晶体管，以进一步改善电流源的动态范围。 本发明在时钟发生器电路中具有特定的应用，其中其减小的漏电流特性和改善的动态范围有助于减少时钟抖动。

公开(公告)号：US06271716B1

公开(公告)日：2001-08-07

申请号：US09220709

申请日：1998-12-21

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： G05F110

CPC分类号： H03L7/0895 ,  G05F3/222 ,  H03L7/0896

摘要： A current source circuit for providing a stable current into a filter element of a phase-lock-loop circuit of a clock generator. The current source circuit comprises a first resistor coupled to a voltage supply. The emitter of a first transistor is coupled to the first resistor; the base is coupled to a bias voltage, and the collector is coupled to a capacitor. The capacitor forms part of the filter of the phase-lock-loop circuit. Current flows from the voltage supply through the first resistor and first transistor into the capacitor. A second transistor has a collector coupled to the capacitor; a base; and an emitter coupled to ground via a second resistor. The second transistor and resistor causes a fixed amount of current to be sinked from the capacitor. Leakage current flowing out of the capacitor due to the inherent Rcb impedance associated with the second transistor is directed to a path provided by a third transistor. The third transistor has an emitter coupled to the base of the second transistor and a collector coupled to the emitter of the first transistor. The third transistor directs the Rcb leakage current inherent to the second transistor back into the capacitor. Thereby, the Rcb leakage current flowing out from the capacitor is canceled by the current flowing back into the capacitor via the third and first transistors. This produces a more stable current, and hence, more stable voltage being maintained by the capacitor. A more stable voltage means that the capacitor can be made smaller. In turn, this enables the phase-lock-loop to be fabricated on-chip with the rest of the clock generator, thereby minimizing its susceptibility to external noise and interferences. Furthermore, a more stable voltage across the filter element of the phase-lock-loop reduces unwanted jitter in the clock signal.

摘要翻译： 一种用于向时钟发生器的锁相环电路的滤波器元件提供稳定电流的电流源电路。 电流源电路包括耦合到电压源的第一电阻器。 第一晶体管的发射极耦合到第一电阻器; 基极耦合到偏置电压，并且集电极耦合到电容器。 电容器形成锁相环电路滤波器的一部分。 电流从电源通过第一电阻和第一晶体管流入电容器。 第二晶体管具有耦合到电容器的集电极; 一个基地 以及通过第二电阻器耦合到地的发射极。 第二晶体管和电阻使固定电流从电容器吸收。 由于与第二晶体管相关联的固有Rcb阻抗而流出电容器的泄漏电流被引导到由第三晶体管提供的路径。 第三晶体管具有耦合到第二晶体管的基极的发射极和耦合到第一晶体管的发射极的集电极。 第三晶体管将第二晶体管固有的Rcb漏电流引导回电容器。 因此，从电容器流出的Rcb漏电流通过经由第三和第一晶体管流回电容器的电流而被抵消。 这产生更稳定的电流，因此由电容器维持更稳定的电压。 更稳定的电压意味着电容器可以做得更小。 反过来，这使得锁相环能够与时钟发生器的其余部分片上制造，从而最小化其对外部噪声和干扰的敏感性。 此外，锁相环路的滤波器元件两端的更稳定的电压降低了时钟信号中的不必要的抖动。

公开(公告)号：US06188268B1

公开(公告)日：2001-02-13

申请号：US09183452

申请日：1998-10-30

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： G05F110

CPC分类号： H03L7/0896 ,  G05F3/222 ,  H03L7/0895

摘要： A low side, low voltage current sink circuit having improved output impedance to reduce effects of leakage current. A current sink circuit is described having a transistor having its emitter coupled to an emitter degeneration resistor which is coupled to the low side (e.g., ground) of a power supply. The output of the current sink is taken at the collector of the transistor. In one embodiment, the transistor is an NPN transistor device. The base of the transistor is coupled to the output of an operational amplifier. One input of the operational amplifier is coupled in a feedback loop to the emitter of the transistor. A direct current bias voltage is applied to the other input of the operational amplifier. In this arrangement, the output impedance (R″o) of the current is sink is based on the open loop gain of the operational amplifier (e.g., about 35 dB) and is therefore orders of magnitude larger than the output impedance of other prior art current sink designs. The novel design limits the voltage drop over the emitter degeneration resistor thereby increasing the differential voltage swing at the collector of the transistor for low power applications. The present invention finds particular application within a clock generator circuit where its reduced leakage current properties and improved dynamic range help to reduce clock jitter in the clock generation circuit.

摘要翻译： 一种具有改善的输出阻抗以降低泄漏电流的影响的低侧，低压电流吸收电路。 描述了一种电流吸收电路，其具有耦合到电源的低侧（例如，接地）的发射极退化电阻的发射极的晶体管。 电流吸收器的输出在晶体管的集电极处获取。 在一个实施例中，晶体管是NPN晶体管器件。 晶体管的基极耦合到运算放大器的输出端。 运算放大器的一个输入端以反馈回路耦合到晶体管的发射极。 直流偏置电压施加到运算放大器的另一个输入端。 在这种布置中，电流的输出阻抗（R''o）是基于运算放大器的开环增益（例如，大约35dB），并且因此比其它先前的输出阻抗大一个数量级 艺术潮流设计。 新颖的设计限制了发射极退化电阻上的电压降，从而增加了用于低功率应用的晶体管集电极上的差分电压摆幅。 本发明在时钟发生器电路中具有特别的应用，其中其减小的漏电流特性和改善的动态范围有助于减少时钟产生电路中的时钟抖动。

公开(公告)号：US6064274A

公开(公告)日：2000-05-16

申请号：US219196

申请日：1998-12-21

申请人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

发明人： Mehrdad Nayebi ,  Stephen D. Edwards ,  Phil Shapiro

IPC分类号： G05F3/22 ,  H03L7/089 ,  H03L7/08 ,  G05F1/10 ,  G05F1/46 ,  H03L7/085

CPC分类号： H03L7/0896 ,  H03L7/0895 ,  G05F3/222

摘要： A current source circuit for providing a stable current into a filter element of a phase-lock-loop circuit of a clock generator. The current source circuit comprises a first resistor coupled to a voltage supply. The emitter of a first transistor is coupled to the first resistor; the collector is coupled to a capacitor which is part of the filter elements of the phase-lock-loop. Current flows from the voltage supply through the first resistor and first transistor into the capacitor. Leakage current flowing out of the capacitor due to the inherent Rcb impedance associated with the first transistor is directed to a path provided by a second transistor. The second transistor has an emitter coupled to the base of the first transistor and a collector coupled to the capacitor. The second transistor is biased such that the Rcb leakage current is directed back into the capacitor. Thereby, the Rcb leakage current flowing out from the capacitor is canceled by the current flowing back into the capacitor via the second transistor. This produces a more stable current, and hence, more stable voltage being maintained by the capacitor. A more stable voltage means that the capacitor can be made smaller. In turn, this enables the phase-lock-loop to be fabricated on-chip with the rest of the clock generator, thereby minimizing its susceptibility to external noise and interferences. Furthermore, a more stable voltage across the filter element of the phase-lock-loop reduces unwanted jitter in the clock signal.

摘要翻译： 一种用于向时钟发生器的锁相环电路的滤波器元件提供稳定电流的电流源电路。 电流源电路包括耦合到电压源的第一电阻器。 第一晶体管的发射极耦合到第一电阻器; 集电极耦合到作为锁相环的滤波器元件的一部分的电容器。 电流从电源通过第一电阻和第一晶体管流入电容器。 由于与第一晶体管相关联的固有Rcb阻抗而流出电容器的泄漏电流被引导到由第二晶体管提供的路径。 第二晶体管具有耦合到第一晶体管的基极的发射极和耦合到电容器的集电极。 第二晶体管被偏置，使得Rcb漏电流被引导回到电容器中。 因此，从电容器流出的Rcb漏电流通过第二晶体管流回到电容器的电流被抵消。 这产生更稳定的电流，因此由电容器维持更稳定的电压。 更稳定的电压意味着电容器可以做得更小。 反过来，这使得锁相环能够与时钟发生器的其余部分片上制造，从而最小化其对外部噪声和干扰的敏感性。 此外，锁相环路的滤波器元件上的更稳定的电压减少了时钟信号中的不必要的抖动。