Method for simplified closed-loop antenna tuning
    2.
    发明授权
    Method for simplified closed-loop antenna tuning 有权
    简化闭环天线调谐方法

    公开(公告)号:US09401738B2

    公开(公告)日:2016-07-26

    申请号:US14799413

    申请日:2015-07-14

    IPC分类号: H04B1/40 H01Q1/50 H01Q5/335

    摘要: A method of closed-loop antenna tuning (CLAT) search strategy based on maximum Relative Transducer Gain (RTG) is proposed. A search region that account for TX input mismatch and forward voltage gain is pre-computed. The search region that is independent of antenna load can be pre-computed to reduce the computation complexity. The Maximum RTG is searched by estimating antenna S-parameters corresponding to a good load match. The search is conducted between the peak forward voltage gain and the best load match. Global optimal with reasonable RTG can be found with limited number of iterations. The transmitter search region can further be constrained by the receiver path mismatching.

    摘要翻译: 提出了一种基于最大相对传感器增益(RTG)的闭环天线调谐(CLAT)搜索策略。 预先计算了考虑到TX输入失配和正向电压增益的搜索区域。 可以预先计算独立于天线负载的搜索区域,以减少计算复杂度。 通过估计对应于良好负载匹配的天线S参数来搜索最大RTG。 搜索在峰值正向电压增益和最佳负载匹配之间进行。 可以用有限的迭代次数找到具有合理RTG的全局最优化。 发射机搜索区域可以进一步受到接收机路径不匹配的约束。

    Method and apparatus for calibrating an envelope tracking system
    3.
    发明授权
    Method and apparatus for calibrating an envelope tracking system 有权
    用于校准包络跟踪系统的方法和装置

    公开(公告)号:US09118366B2

    公开(公告)日:2015-08-25

    申请号:US13798099

    申请日:2013-03-13

    摘要: A method of calibrating an envelope tracking system for a supply voltage for a power amplifier module within a radio frequency (RF) transmitter module of a wireless communication unit. The method includes, within at least one signal processing module of the wireless communication unit, applying a training signal having an envelope that varies with time to an input of the RF transmitter module, receiving at least an indication of instantaneous output signal values for the power amplifier module in response to the training signal, calculating instantaneous gain values based at least partly on the received output power values, and adjusting a mapping function between an instantaneous envelope of a waveform signal to be amplified by the power amplifier module and the power amplifier module supply voltage to achieve a constant power amplifier module gain.

    摘要翻译: 一种校准用于无线通信单元的射频(RF)发射机模块内的功率放大器模块的电源电压的包络跟踪系统的方法。 该方法包括在无线通信单元的至少一个信号处理模块内,将具有随时间变化的包络的训练信号应用于RF发射机模块的输入,至少接收用于功率的瞬时输出信号值的指示 放大器模块,响应于训练信号,至少部分地基于所接收的输出功率值来计算瞬时增益值,并且调整要由功率放大器模块放大的波形信号的瞬时包络和功率放大器模块之间的映射函数 电源电压实现恒功率放大器模块增益。

    Quadrature transmitter, wireless communication unit, and method for spur suppression

    公开(公告)号:US10419046B2

    公开(公告)日:2019-09-17

    申请号:US16002355

    申请日:2018-06-07

    IPC分类号: H04B1/04 H04B1/525 H04L27/00

    摘要: A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

    TRANSFORMER WITH TWO TRANSFORMATION RATIO
    6.
    发明申请
    TRANSFORMER WITH TWO TRANSFORMATION RATIO 有权
    具有两个变换比的变压器

    公开(公告)号:US20160118180A1

    公开(公告)日:2016-04-28

    申请号:US14923479

    申请日:2015-10-27

    IPC分类号: H01F27/28

    摘要: A transformer includes a first winding conductor and a second winding conductor, magnetically coupled to the first winding conductor. A first transformation ratio is achieved between the second winding conductor and the first winding conductor. A first distance between the first winding conductor and the second winding conductor is higher than a distance threshold, and accordingly, a first coupling factor between the first winding conductor and the second winding conductor is lower than a coupling factor threshold.

    摘要翻译: 变压器包括磁耦合到第一绕组导体的第一绕组导体和第二绕组导体。 在第二绕组导体和第一绕组导体之间实​​现第一变换比。 第一绕组导体和第二绕组导体之间的第一距离高于距离阈值,因此第一绕组导体和第二绕组导体之间的第一耦合因子低于耦合因子阈值。

    SQUARING CIRCUIT, INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR
    7.
    发明申请
    SQUARING CIRCUIT, INTEGRATED CIRCUIT, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR 有权
    整流电路,集成电路,无线通信单元及其方法

    公开(公告)号:US20140084987A1

    公开(公告)日:2014-03-27

    申请号:US14092958

    申请日:2013-11-28

    IPC分类号: G06G7/20

    CPC分类号: G06G7/20 G06G7/164 H04B17/13

    摘要: A squaring circuit has current mode triplet metal oxide semiconductor (MOS) devices, including a first MOS device, a second MOS device and a third MOS device each having a source operably coupled to a first current source; and a fourth MOS device, a fifth MOS device and a sixth MOS device each having a source operably coupled to a second current source. The drain of first and fourth MOS device is operably coupled to a first supply, the drain of second and fifth MOS device is operably coupled to a first differential output port and the drain of third and sixth MOS device is operably coupled to a second differential output port. The gate of first, second and sixth MOS device is connected to a first differential input port, and the gate of third, fourth and fifth MOS device is connected to a second differential input port.

    摘要翻译: 平方电路具有电流模式三重态金属氧化物半导体(MOS)器件,包括第一MOS器件,第二MOS器件和第三MOS器件,每个MOS器件具有可操作地耦合到第一电流源的源极; 以及第四MOS器件,第五MOS器件和第六MOS器件,每个具有可操作地耦合到第二电流源的源极。 第一和第四MOS器件的漏极可操作地耦合到第一电源,第二和第五MOS器件的漏极可操作地耦合到第一差分输出端口,并且第三和第六MOS器件的漏极可操作地耦合到第二差分输出 港口。 第一,第二和第六MOS器件的栅极连接到第一差分输入端口,第三,第四和第五MOS器件的栅极连接到第二差分输入端口。

    QUADRATURE TRANSMITTER, WIRELESS COMMUNICATION UNIT, AND METHOD FOR SPUR SUPPRESSION

    公开(公告)号:US20170346510A1

    公开(公告)日:2017-11-30

    申请号:US15367439

    申请日:2016-12-02

    IPC分类号: H04B1/04 H04L25/49

    CPC分类号: H04B1/0475 H04L25/49

    摘要: A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path. The first set of quadrature signals is a substantially 45° phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45° phase shifted version of the second set of quadrature LO signals.

    SYSTEM COMPRISING A MASTER DEVICE AND A SLAVE DEVICE HAVING MULTIPLE INTEGRATED CIRCUIT DIE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR

    公开(公告)号:US20170192918A1

    公开(公告)日:2017-07-06

    申请号:US15177557

    申请日:2016-06-09

    IPC分类号: G06F13/364 G06F13/42

    CPC分类号: G06F13/364 G06F13/4291

    摘要: A system is described that comprises: a master device and a slave device. The slave device comprises: a first die comprising an interface comprising a decoder configured to support a MIPI™ RFFE slave protocol; at least one second die comprising a simplified address decoder, operably coupled to the first die; and a shared control bus that is configured to support at least a clock signal and a data signal shared between the master device and the at least one second die on the slave device. The interface of the first die is configured to generate at least one circuit enable signal, routed to the at least one second die. The simplified address decoder is configured to process the clock signal and the data signal in response to the at least one circuit enable signal. In this manner, by partitioning the protocol handling to a protocol decoder in a first die, and one or more second die that support a simplified address decoder, the first die is able to individually select the die to receive a data frame by generating and routing the enable signal.