公开(公告)号：US10027316B2

公开(公告)日：2018-07-17

申请号：US15243237

申请日：2016-08-22

Applicant: MediaTek Inc.

Inventor： Yi-Feng Chen ,  Ya-Shih Huang ,  Chun-Sheng Huang ,  Yiwei Chen

IPC: H03K5/15 ,  H03K5/135 ,  H03K5/00

Abstract: A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

公开(公告)号：US10177147B2

公开(公告)日：2019-01-08

申请号：US15134897

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Yiwei Chen

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/118

Abstract: A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.