公开(公告)号：US20160336316A1

公开(公告)日：2016-11-17

申请号：US15134897

申请日：2016-04-21

Applicant: MediaTek Inc.

Inventor： Yiwei CHEN

IPC: H01L27/092 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L2027/11837

Abstract: A semiconductor device is provided. Gates of first PMOS and NMOS transistors are coupled together for receiving an input signal. Gates of second PMOS and NMOS transistors are coupled together. Gates of third PMOS and NMOS transistors are coupled together. Gates of fourth PMOS and NMOS transistors are coupled together. Drains of fourth PMOS and NMOS transistors are coupled together for providing an output signal. When the first, second, third and fourth NMOS transistors are connected in parallel and the first, second, third and fourth PMOS transistors are connected in parallel, the output signal is provided according to the input signal and a first logic function. When the first and second NMOS transistors are connected in serial and the first and second PMOS transistors are connected in serial, the output signal is provided according to the input signal and a second logic function.

Abstract translation: 提供半导体器件。 第一PMOS和NMOS晶体管的栅极耦合在一起以接收输入信号。 第二PMOS和NMOS晶体管的栅极耦合在一起。 第三PMOS和NMOS晶体管的栅极耦合在一起。 第四PMOS和NMOS晶体管的栅极耦合在一起。 第四PMOS和NMOS晶体管的漏极耦合在一起以提供输出信号。 当第一，第二，第三和第四NMOS晶体管并联连接时，并联连接第一，第二，第三和第四PMOS晶体管，根据输入信号和第一逻辑功能提供输出信号。 当第一和第二NMOS晶体管串联连接并且第一和第二PMOS晶体管串联时，根据输入信号和第二逻辑功能提供输出信号。

公开(公告)号：US20170063358A1

公开(公告)日：2017-03-02

申请号：US15243237

申请日：2016-08-22

Applicant: MediaTek Inc.

Inventor： Yi-Feng CHEN ,  Ya-Shih HUANG ,  Chun-Sheng HUANG ,  Yiwei CHEN

IPC: H03K5/15

CPC classification number: H03K5/15 ,  H03K5/135 ,  H03K2005/00019

Abstract: A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

Abstract translation: 提供时钟缓冲电路。 时钟缓冲电路接收输入时钟信号并产生延迟时钟信号。 时钟缓冲电路包括输入电路，输出电路，第一延迟路径和第二延迟路径。 输入电路接收输入时钟信号，并根据输入时钟信号产生输出时钟信号。 输出电路产生延迟时钟信号。 第一延迟路径耦合在输入电路和输出电路之间。 第二延迟路径耦合在输入电路和输出电路之间。 输入电路根据控制信号选择性地将输出时钟信号提供给第一和第二延迟路径中的第一特定延迟路径。 输出电路接收通过第一特定延迟路径的输出时钟信号并输出​​延迟时钟信号。

公开(公告)号：US20180203067A1

公开(公告)日：2018-07-19

申请号：US15692048

申请日：2017-08-31

Applicant: MEDIATEK INC.

Inventor： Yiwei CHEN

IPC: G01R31/3185 ,  G11C29/32 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318536 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318552 ,  G01R31/31858 ,  G11C29/32 ,  G11C29/46 ,  G11C2029/3202

Abstract: A scan chain circuit is provided. The scan chain circuit includes first and second scan flip-flops and a clock generator. Each of the first and second scan flip-flops has a data-in terminal, a scan-in terminal, a clock terminal, and a data-out terminal. The clock terminals of the first and second scan flip-flop receive first and second clock signals respectively. The data-in terminal of the second scan flip-flop is coupled to the data-out terminal of the first scan flip-flop. During a scan shift cycle of the test mode, an enable pulse of a second clock-enable signal is delayed from an enable pulse of a first clock-enable signal, and the clock generator generates the first clock signal according to the scan clock signal and the first clock-enable signal and further generates the second clock signal according to the scan clock signal and the second clock-enable signal.