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公开(公告)号：US09898288B2
公开(公告)日：2018-02-20
申请号：US14982257
申请日：2015-12-29
Applicant: MediaTek Inc.
Inventor： Yan-Hong Lu , Jia-Yang Chang , Pao-Hung Kuo , Chia-Chi Chang , Pei-Kuei Tsung
IPC: G06F9/30
CPC classification number: G06F9/30061 , G06F9/30 , G06F9/3009
Abstract: A computer-implemented method of executing an instruction sequence with a recursive function call of a plurality of threads within a thread group in a Single-Instruction-Multiple-Threads (SIMT) system is provided. Each thread is provided with a function call counter (FCC), an active mask, an execution mask and a per-thread program counter (PTPC). The instruction sequence with the recursive function call is executed by the threads in the thread group according to a program counter (PC) indicating a target. Upon executing the recursive function call, for each thread, the active mask is set according to the PTPC and the target indicated by the PC, the FCC is determined when entering or returning from the recursive function call, the execution mask is determined according to the FCC and the active mask. It is determined whether an execution result of the recursive function call takes effects according to the execution mask.
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2.发明申请GRAPHICS PROCESSING CIRCUIT HAVING SECOND VERTEX SHADER CONFIGURED TO REUSE OUTPUT OF FIRST VERTEX SHADER AND/OR PROCESS REPACKED VERTEX THREAD GROUP AND RELATED GRAPHICS PROCESSING METHOD THEREOF 有权具有配置的第二VERTEX SHADER的图形处理电路重新产生第一VERTEX SHADER的输出和/或处理重新编译的VERTEX线程组及其相关图形处理方法公开(公告)号：US20160042560A1
公开(公告)日：2016-02-11
申请号：US14454738
申请日：2014-08-08
Applicant: MEDIATEK INC.
Inventor： Jia-Yang Chang
CPC classification number: G06T15/80 , G06T1/20 , G06T1/60 , G06T15/005
Abstract: A graphics processing circuit includes a buffer, a first vertex shader, and a second vertex shader. The first vertex shader generates at least coordinate values of a plurality of vertices to the buffer. The second vertex shader reads at least a portion of buffered coordinate values from the buffer, and reuses at least the portion of the buffered coordinate values to generate a value of at least one user-defined variable.
Abstract translation: 图形处理电路包括缓冲器，第一顶点着色器和第二顶点着色器。 第一顶点着色器至少产生多个顶点的坐标值到缓冲器。 第二顶点着色器从缓冲器中读取缓冲坐标值的至少一部分，并重新使用缓冲的坐标值的至少一部分来生成至少一个用户定义变量的值。
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公开(公告)号：US10318307B2
公开(公告)日：2019-06-11
申请号：US14741505
申请日：2015-06-17
Applicant: MediaTek Inc.
Inventor： Jia-Yang Chang
Abstract: A Single-Instruction-Multiple-Treads (SIMT) computing system includes multiple processors and a scheduler to schedule multiple threads to each of the processors. Each processor includes a scalar unit to provide a scalar lane for scalar execution and vector units to provide N parallel lanes for vector execution. During execution time, a processor detects that an instruction of N threads has been predicted by a compiler to have (N−M) inactive threads and the same source operands for M active threads, where N>M≥1. Upon the detection, the instruction is sent to the scalar unit for scalar execution.
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4.发明授权Graphics processing circuit having second vertex shader configured to reuse output of first vertex shader and/or process repacked vertex thread group and related graphics processing method thereof 有权具有第二顶点着色器的图形处理电路被配置为重新使用第一顶点着色器和/或处理重新包装的顶点线程组的输出及其相关的图形处理方法公开(公告)号：US09424686B2
公开(公告)日：2016-08-23
申请号：US14454738
申请日：2014-08-08
Applicant: MEDIATEK INC.
Inventor： Jia-Yang Chang
CPC classification number: G06T15/80 , G06T1/20 , G06T1/60 , G06T15/005
Abstract: A graphics processing circuit includes a buffer, a first vertex shader, and a second vertex shader. The first vertex shader generates at least coordinate values of a plurality of vertices to the buffer. The second vertex shader reads at least a portion of buffered coordinate values from the buffer, and reuses at least the portion of the buffered coordinate values to generate a value of at least one user-defined variable.
Abstract translation: 图形处理电路包括缓冲器，第一顶点着色器和第二顶点着色器。 第一顶点着色器至少产生多个顶点的坐标值到缓冲器。 第二顶点着色器从缓冲器中读取缓冲坐标值的至少一部分，并重新使用缓冲的坐标值的至少一部分来生成至少一个用户定义变量的值。
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