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公开(公告)号：US20150162171A9
公开(公告)日：2015-06-11
申请号：US13524859
申请日：2012-06-15
CPC分类号： C23C14/564 , H01J37/32651 , H01J37/3405 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
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公开(公告)号：US20090260982A1
公开(公告)日：2009-10-22
申请号：US12423444
申请日：2009-04-14
IPC分类号： C23C14/34
CPC分类号： C23C16/4585 , C23C14/34 , C23C14/50 , C23C14/564 , H01J37/32623 , H01J37/32633 , H01J37/3408 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
摘要翻译： 本文描述的实施例通常涉及用于半导体处理室的部件，用于半导体处理室的处理套件和具有处理套件的半导体处理室。 在一个实施例中，提供了用于环绕溅射靶的底部屏蔽件和衬底支撑件。 下屏蔽包括具有第一直径的圆柱形外带，其尺寸被设计成围绕溅射靶的溅射表面和衬底支撑件，该圆柱形带包括围绕溅射靶的溅射表面的顶壁和围绕溅射靶的底壁 衬底支撑件，包括搁置表面并从圆柱形外带径向向外延伸的支撑凸缘，从圆柱形带的底壁径向向内延伸的底板，以及与基板耦合并部分围绕外围的圆柱形内带 基板支撑的边缘。
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公开(公告)号：US08696878B2
公开(公告)日：2014-04-15
申请号：US13457441
申请日：2012-04-26
IPC分类号： C25B9/00 , C23C14/00 , C25B11/00 , C25B13/00 , B05C11/11 , C23C16/00 , C23C16/458 , C23C14/34 , C23C14/50 , C23C14/56 , H01J37/32 , H01J37/34
CPC分类号： C23C16/4585 , C23C14/34 , C23C14/50 , C23C14/564 , H01J37/32623 , H01J37/32633 , H01J37/3408 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
摘要翻译： 本文描述的实施例通常涉及用于半导体处理室的部件，用于半导体处理室的处理套件和具有处理套件的半导体处理室。 在一个实施例中，提供了用于环绕溅射靶的底部屏蔽件和衬底支撑件。 下屏蔽包括具有第一直径的圆柱形外带，其尺寸被设计成围绕溅射靶的溅射表面和衬底支撑件，该圆柱形带包括围绕溅射靶的溅射表面的顶壁和围绕溅射靶的底壁 衬底支撑件，包括搁置表面并从圆柱形外带径向向外延伸的支撑凸缘，从圆柱形带的底壁径向向内延伸的底板，以及与基板耦合并部分围绕外围的圆柱形内带 基板支撑的边缘。
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公开(公告)号：US09062379B2
公开(公告)日：2015-06-23
申请号：US13524859
申请日：2012-06-15
CPC分类号： C23C14/564 , H01J37/32651 , H01J37/3405 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
摘要翻译： 本文描述的实施例通常涉及用于半导体处理室的部件，用于半导体处理室的处理套件和具有处理套件的半导体处理室。 在一个实施例中，提供了用于环绕溅射靶的底部屏蔽件和衬底支撑件。 下屏蔽包括具有第一直径的圆柱形外带，其尺寸被设计成围绕溅射靶的溅射表面和衬底支撑件，该圆柱形带包括围绕溅射靶的溅射表面的顶壁和围绕溅射靶的底壁 衬底支撑件，包括搁置表面并从圆柱形外带径向向外延伸的支撑凸缘，从圆柱形带的底壁径向向内延伸的底板，以及与基板耦合并部分围绕外围的圆柱形内带 基板支撑的边缘。
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公开(公告)号：US20130334038A1
公开(公告)日：2013-12-19
申请号：US13524859
申请日：2012-06-15
IPC分类号： C23C14/34
CPC分类号： C23C14/564 , H01J37/32651 , H01J37/3405 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
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公开(公告)号：US20120211359A1
公开(公告)日：2012-08-23
申请号：US13457441
申请日：2012-04-26
IPC分类号： C23C14/34
CPC分类号： C23C16/4585 , C23C14/34 , C23C14/50 , C23C14/564 , H01J37/32623 , H01J37/32633 , H01J37/3408 , H01J37/3441
摘要： Embodiments described herein generally relate to components for a semiconductor processing chamber, a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a process kit. In one embodiment a lower shield for encircling a sputtering target and a substrate support is provided. The lower shield comprises a cylindrical outer band having a first diameter dimensioned to encircle the sputtering surface of the sputtering target and the substrate support, the cylindrical band comprising a top wall that surrounds a sputtering surface of a sputtering target and a bottom wall that surrounds the substrate support, a support ledge comprising a resting surface and extending radially outward from the cylindrical outer band, a base plate extending radially inward from the bottom wall of the cylindrical band, and a cylindrical inner band coupled with the base plate and partially surrounding a peripheral edge of the substrate support.
摘要翻译： 本文描述的实施例通常涉及用于半导体处理室的部件，用于半导体处理室的处理套件和具有处理套件的半导体处理室。 在一个实施例中，提供了用于环绕溅射靶的底部屏蔽件和衬底支撑件。 下屏蔽包括具有第一直径的圆柱形外带，其尺寸被设计成围绕溅射靶的溅射表面和衬底支撑件，该圆柱形带包括围绕溅射靶的溅射表面的顶壁和围绕溅射靶的底壁 衬底支撑件，包括搁置表面并从圆柱形外带径向向外延伸的支撑凸缘，从圆柱形带的底壁径向向内延伸的底板，以及与基板耦合并部分围绕外围的圆柱形内带 基板支撑的边缘。
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公开(公告)号：US07718045B2
公开(公告)日：2010-05-18
申请号：US11426775
申请日：2006-06-27
IPC分类号： C23C14/34
CPC分类号： H01J37/3405 , H01J37/32623 , H01J2237/0206 , H01J2237/026
摘要： The invention generally provides a ground shield for use in a physical vapor deposition (PVD) chamber. In one embodiment, a ground shield includes a generally cylindrical body comprising an outer wall, an inner upper wall, an inner lower wall having a diameter less than a diameter of the inner upper wall and a reentrant feature coupling the upper and inner lower walls. The reentrant feature advantageously prevents arching between the shield and target, which promotes greater process uniformity and repeatability along with longer chamber component service life.
摘要翻译： 本发明通常提供用于物理气相沉积（PVD）室的接地屏蔽。 在一个实施例中，接地屏蔽包括大致圆柱形的主体，其包括外壁，内上壁，直径小于内上壁的直径的内下壁和连接上下壁的可重入特征。 可折入特征有利于防止护罩和靶之间的拱形，这促进了更大的工艺均匀性和重复性以及更长的腔室部件使用寿命。
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公开(公告)号：US20070295602A1
公开(公告)日：2007-12-27
申请号：US11426775
申请日：2006-06-27
IPC分类号： C23C14/00
CPC分类号： H01J37/3405 , H01J37/32623 , H01J2237/0206 , H01J2237/026
摘要： The invention generally provides a ground shield for use in a physical vapor deposition (PVD) chamber. In one embodiment, a ground shield includes a generally cylindrical body comprising an outer wall, an inner upper wall, an inner lower wall having a diameter less than a diameter of the inner upper wall and a reentrant feature coupling the upper and inner lower walls. The reentrant feature advantageously prevents arching between the shield and target, which promotes greater process uniformity and repeatability along with longer chamber component service life.
摘要翻译： 本发明通常提供用于物理气相沉积（PVD）室的接地屏蔽。 在一个实施例中，接地屏蔽包括大致圆柱形的主体，其包括外壁，内上壁，直径小于内上壁的直径的内下壁和连接上下壁的可重入特征。 可折入特征有利于防止护罩和靶之间的拱形，这促进了更大的工艺均匀性和重复性以及更长的腔室部件使用寿命。
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9.发明申请OXYGEN CONTROLLED PVD ALN BUFFER FOR GAN-BASED OPTOELECTRONIC AND ELECTRONIC DEVICES 审中-公开用于基于GAN的光电和电子设备的氧气控制PVD ALN缓冲器公开(公告)号：US20160035937A1
公开(公告)日：2016-02-04
申请号：US14884251
申请日：2015-10-15
申请人： Mingwei Zhu , Nag B. Patibandla , Rongjun Wang , Daniel Lee Diehl , Vivek Agrawal , Anantha Subramani
发明人： Mingwei Zhu , Nag B. Patibandla , Rongjun Wang , Daniel Lee Diehl , Vivek Agrawal , Anantha Subramani
CPC分类号： H01L33/12 , H01J37/32467 , H01J37/32724 , H01J37/3405 , H01J37/347 , H01L29/2003 , H01L31/1856 , H01L33/007 , H01L33/0075 , Y02E10/544
摘要： Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.
摘要翻译： 描述了用于GaN基光电子和电子器件的氧控PVD PVD缓冲器。 还描述了以氧控制方式形成GaN基光电子和电子器件的PVD AlN缓冲液的方法。 在一个示例中，形成用于GaN基光电子或电子器件的氮化铝（AlN）缓冲层的方法包括在衬底上方的AlN层的反应溅射，所述反应性溅射涉及使物理气相沉积 （PVD）室，其含有含氮气体或基于含氮气体的等离子体。 该方法还包括将氧气掺入到AlN层中。
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10.发明授权公开(公告)号：US09224582B2
公开(公告)日：2015-12-29
申请号：US11947459
申请日：2007-11-29
申请人： John Forster , Anantha Subramani , Wei D. Wang
发明人： John Forster , Anantha Subramani , Wei D. Wang
CPC分类号： H01J37/32477 , C23C14/34 , H01J37/32495 , H01L21/02043 , H01L21/67005
摘要： A method and apparatus are described for reducing particle contamination in a plasma processing chamber. In one embodiment, a pasting disk is provided which includes a disk-shaped base of high-resistivity material that has an electrically conductive pasting material layer applied to a top surface of the base so that the pasting material layer partially covers the top surface of the base. The pasting disk is sputter etched to deposit conductive pasting material over a wide area on the interior surfaces of a plasma processing chamber while minimizing deposition on dielectric components that are used to optimize the sputter etch process during substrate processing.
摘要翻译： 描述了一种用于减少等离子体处理室中的颗粒污染的方法和装置。 在一个实施例中，提供了一种粘贴盘，其包括高电阻率材料的盘形基底，其具有施加到基部的顶表面的导电粘贴材料层，使得粘贴材料层部分地覆盖基底的顶表面 基础。 溅射蚀刻粘贴盘以在等离子体处理室的内表面上的广泛区域上沉积导电粘贴材料，同时最小化用于在衬底处理期间优化溅射蚀刻工艺的介电部件上的沉积。
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