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    Multilayer electronic component
    1.
    发明授权
    Multilayer electronic component 有权

    公开(公告)号：US12100559B2

    公开(公告)日：2024-09-24

    申请号：US18328258

    申请日：2023-06-02

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tatsuya Izumi ,  Tomotaka Hirata

    IPC: H01G4/30 ,  C04B35/057 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

    CPC classification number: H01G4/30 ,  C04B35/057 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1236 ,  C04B2235/3206 ,  C04B2235/3208

    Abstract: A multilayer electronic component that includes a stacked body having therein a plurality of dielectric layers including a CZ-based perovskite phase and an element M2, a plurality of internal electrode layers including Ni, and an interface layer including the element M2 in at least a portion of an interface with the plurality of internal electrode layers. Element M2 is an element that has a binding energy between the CZ-based perovskite phase and Ni via the element M2 of less than or equal to −12.3 eV by first-principles calculation using a pseudopotential method. When amounts of elements included in the dielectric layers are expressed as parts by mol, a ratio m2 of an amount of the element M2 to an amount of the Zr in the interface layer is 0.03≤m2≤0.25.

    Laminated ceramic capacitor
    2.
    发明授权
    Laminated ceramic capacitor 有权
    层压陶瓷电容器

    公开(公告)号：US09460852B2

    公开(公告)日：2016-10-04

    申请号：US14210786

    申请日：2014-03-14

    Applicant: MURATA MANUFACTURING CO., LTD.

    Inventor： Hiroyuki Wada ,  Kohei Shimada ,  Kenji Takagi ,  Tomomi Koga ,  Tomotaka Hirata ,  Hitoshi Nishimura ,  Hiroki Awata ,  Sui Uno

    IPC: H01G4/30 ,  H01G4/06 ,  H01G4/12

    CPC classification number: H01G4/1227 ,  H01G4/1218 ,  H01G4/30

    Abstract: A laminated ceramic capacitor having a laminated body composed of a plurality of ceramic layers for inner layers; a plurality of internal electrodes at the interfaces between the plurality of ceramic layers for inner layers; and a plurality of ceramic layers for outer layers, provided on the top and bottom so as to sandwich the plurality of ceramic layers for inner layers. The ceramic layers for inner layers are composed of a material containing a multiple oxide including an alkaline-earth metal. The ceramic layers for outer layers respectively have TiO2 ceramic layers containing TiO2 as their main constituent for certain layers including the outermost layers, and multiple oxide ceramic layers containing a multiple oxide including an alkaline-earth metal for the other layers.

    Abstract translation: 一种层叠陶瓷电容器，具有由多个内层用陶瓷层构成的层叠体， 在所述多个用于内层的陶瓷层之间的界面处的多个内部电极; 以及多个用于外层的陶瓷层，设置在顶部和底部，以便将多个陶瓷层夹在内层中。 内层的陶瓷层由含有碱土类金属的多重氧化物的材料构成。 用于外层的陶瓷层分别具有包含TiO 2作为其主要成分的TiO 2陶瓷层，其中包括最外层的某些层，以及包含用于其它层的包含碱土金属的多重氧化物的多个氧化物陶瓷层。

    LAMINATED CERAMIC CAPACITOR
    3.
    发明申请
    LAMINATED CERAMIC CAPACITOR 有权
    层压陶瓷电容器

    公开(公告)号：US20140285948A1

    公开(公告)日：2014-09-25

    申请号：US14210786

    申请日：2014-03-14

    Applicant: MURATA MANUFACTURING CO., LTD.

    Inventor： Hiroyuki Wada ,  Kohei Shimada ,  Kenji Takagi ,  Koga Tomomi ,  Tomotaka Hirata ,  Hitoshi Nishimura ,  Hiroki Awata ,  Sui Uno

    IPC: H01G4/12

    CPC classification number: H01G4/1227 ,  H01G4/1218 ,  H01G4/30

    Abstract: A laminated ceramic capacitor having a laminated body composed of a plurality of ceramic layers for inner layers; a plurality of internal electrodes at the interfaces between the plurality of ceramic layers for inner layers; and a plurality of ceramic layers for outer layers, provided on the top and bottom so as to sandwich the plurality of ceramic layers for inner layers. The ceramic layers for inner layers are composed of a material containing a multiple oxide including an alkaline-earth metal. The ceramic layers for outer layers respectively have TiO2 ceramic layers containing TiO2 as their main constituent for certain layers including the outermost layers, and multiple oxide ceramic layers containing a multiple oxide including an alkaline-earth metal for the other layers.

    Abstract translation: 一种层叠陶瓷电容器，具有由多个内层用陶瓷层构成的层叠体， 在所述多个用于内层的陶瓷层之间的界面处的多个内部电极; 以及多个用于外层的陶瓷层，设置在顶部和底部，以便将多个陶瓷层夹在内层中。 内层的陶瓷层由含有碱土类金属的多重氧化物的材料构成。 用于外层的陶瓷层分别具有包含TiO 2作为其主要成分的TiO 2陶瓷层，其中包括最外层的某些层，以及包含用于其它层的包含碱土金属的多重氧化物的多个氧化物陶瓷层。

    Dielectric ceramic composition and multilayer ceramic capacitor
    4.
    发明授权
    Dielectric ceramic composition and multilayer ceramic capacitor 有权

    公开(公告)号：US11158457B2

    公开(公告)日：2021-10-26

    申请号：US16659596

    申请日：2019-10-22

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yasuko Ooe ,  Tatsuya Izumi ,  Tomotaka Hirata

    IPC: C04B35/49 ,  H01G4/008 ,  H01G4/12

    Abstract: A dielectric ceramic composition includes, as a main component, a perovskite compound containing Sr and Zr and may contain Ca and/or Ti, further contains Li and Si, and may contain Mn. When a total content of Zr and Ti is 100 parts by mol, a total content (100×m) of parts by mol of Sr and Ca is 0.8≤m≤1.3, a content a of parts by mol of Mn is 0≤a≤10, a content b of parts by mol of Li is 5≤b≤15, a content c of parts by mol of Si is 20≤c≤40, a molar ratio x of Ca/(Sr+Ca) is 0≤x≤0.8, and a molar ratio y of Ti/(Zr+Ti) is 0≤y≤0.5.

    Multilayer ceramic capacitor
    7.
    发明授权
    Multilayer ceramic capacitor 有权
    多层陶瓷电容器

    公开(公告)号：US09042082B2

    公开(公告)日：2015-05-26

    申请号：US14528996

    申请日：2014-10-30

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiroyuki Wada ,  Kohei Shimada ,  Kenji Takagi ,  Tomomi Koga ,  Tomotaka Hirata ,  Hitoshi Nishimura ,  Hiroki Awata ,  Sui Uno

    IPC: H01G4/06 ,  H01G4/228 ,  H01G4/12 ,  H01G4/012 ,  H01G4/224 ,  H01G4/248 ,  H01G4/30

    CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/1209 ,  H01G4/1227 ,  H01G4/1245 ,  H01G4/224 ,  H01G4/248

    Abstract: A multilayer ceramic capacitor includes a ceramic main body including an inner layer portion including third ceramic layers and a plurality of inner electrodes arranged at interfaces between the third ceramic layers, and first and second outer layer portions respectively including first and second ceramic layers, the first and second ceramic layers being arranged vertically so as to sandwich the inner layer portion. The third ceramic layers and the first and second outer layer portions contain a perovskite-type compound represented by ABO3 where A contains one or more of Ba, Sr, and Ca, B contains one or more of Ti, Zr, and Hf, and O represents oxygen) as a main component. Where a rare-earth element concentration (CR) in the third ceramic layers is compared to a rare-earth element concentration (Cr) in outermost layer portions including at least outermost surfaces of the first and second outer layer portions, CR>Cr (inclusive of Cr=0).

    Abstract translation: 多层陶瓷电容器包括陶瓷主体，其包括内层部分，其包括第三陶瓷层和布置在第三陶瓷层之间的界面处的多个内电极以及分别包括第一和第二陶瓷层的第一和第二外层部分， 并且第二陶瓷层垂直布置以夹住内层部分。 第三陶瓷层和第一外层和第二外层部分含有由ABO 3表示的钙钛矿型化合物，其中A含有Ba，Sr和Ca中的一种或多种，​​B包含Ti，Zr和Hf中的一种或多种，​​O 代表氧）作为主要成分。 在将第三陶瓷层中的稀土元素浓度（CR）与至少包含第一和第二外层部分的最外表面的最外层部分中的稀土元素浓度（Cr）进行比较时，CR> Cr（包括 的Cr = 0）。

    Multilayer electronic component
    8.
    发明授权
    Multilayer electronic component 有权

    公开(公告)号：US11710600B2

    公开(公告)日：2023-07-25

    申请号：US16987684

    申请日：2020-08-07

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tatsuya Izumi ,  Tomotaka Hirata

    IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12 ,  C04B35/057

    CPC classification number: H01G4/30 ,  C04B35/057 ,  H01G4/008 ,  H01G4/012 ,  H01G4/1236 ,  C04B2235/3206 ,  C04B2235/3208

    Abstract: A multilayer electronic component that includes a stacked body having therein a plurality of dielectric layers including a CZ-based perovskite phase and an element M1, a plurality of internal electrode layers including Cu, and an interface layer including the element M1 in at least a portion of an interface with the plurality of internal electrode layers. Element M1 is an element that has a binding energy between CZ and Cu via the element M1 of less than or equal to −9.8 eV by first-principles calculation using a pseudopotential method. When amounts of elements included in the dielectric layers are expressed as parts by mol, a ratio m1 of an amount of the element M1 to an amount of the Zr in the interface layer is 0.03≤m1≤0.25.

    MULTILAYER ELECTRONIC COMPONENT
    9.
    发明申请
    MULTILAYER ELECTRONIC COMPONENT 有权

    公开(公告)号：US20210065989A1

    公开(公告)日：2021-03-04

    申请号：US16987684

    申请日：2020-08-07

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Tatsuya Izumi ,  Tomotaka Hirata

    IPC: H01G4/30 ,  H01G4/012 ,  H01G4/008 ,  H01G4/12 ,  C04B35/057

    Abstract: A multilayer electronic component that includes a stacked body having therein a plurality of dielectric layers including a CZ-based perovskite phase and an element M1, a plurality of internal electrode layers including Cu, and an interface layer including the element M1 in at least a portion of an interface with the plurality of internal electrode layers. Element M1 is an element that has a binding energy between CZ and Cu via the element M1 of less than or equal to −9.8 eV by first-principles calculation using a pseudopotential method. When amounts of elements included in the dielectric layers are expressed as parts by mol, a ratio m1 of an amount of the element M1 to an amount of the Zr in the interface layer is 0.03≤m1≤0.25.

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