公开(公告)号：US10768930B2

公开(公告)日：2020-09-08

申请号：US14612104

申请日：2015-02-02

申请人： MIPS Tech, LLC

发明人： Ranganathan Sudhakar

IPC分类号： G06F7/499 ,  G06F9/302 ,  G06F9/40 ,  G06F9/30 ,  G06F9/38 ,  G06F9/355 ,  G06F9/32 ,  G06F7/505

摘要： A method provides for decoding, in a microprocessor, an instruction into data identifying a first register, a second register, an immediate value, and an opcode identifier. The opcode identifier is interpreted as indicating that an arithmetic operation is to be performed on the first register and the second register, and that the microprocessor is to perform a change of control operation in response to the addition of the first register and the second register causing overflow or underflow. The change of control operation is to a location in a program determined based on the immediate value. A processor can be provided with a decoder and other supporting circuitry to implement such method. Overflow/underflow can be checked on word boundaries of a double-word operation.

公开(公告)号：US10671391B2

公开(公告)日：2020-06-02

申请号：US14612090

申请日：2015-02-02

申请人： MIPS Tech, LLC

发明人： Ranganathan Sudhakar ,  Ranjit J Rozario

IPC分类号： G06F9/30 ,  G06F9/34

摘要： In an aspect, a processor supports modeless execution of 64 bit and 32 bit instructions. A Load/Store Unit (LSU) decodes an instruction that without explicit opcode data indicating whether the instruction is to operate in a 32 or 64 bit memory address space. LSU treats the instruction either as a 32 or 64 bit instruction in dependence on values in an upper 32 bits of one or more 64 bit operands supplied to create an effective address in memory. In an example, a 4 GB space addressed by 32-bit memory space is divided between upper and lower portions of a 64-bit address space, such that a 32-bit instruction is differentiated from a 64-bit instruction in dependence on whether an upper 32 bits of one or more operands is either all binary 1 or all binary 0. Such a processor may support decoding of different arithmetic instructions for 32-bit and 64-bit operations.

公开(公告)号：US10540179B2

公开(公告)日：2020-01-21

申请号：US13789467

申请日：2013-03-07

申请人： MIPS Tech, LLC

发明人： Ranganathan Sudhakar ,  Parthiv Pota

IPC分类号： G06F9/30

摘要： A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.