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公开(公告)号：US20240036977A1
公开(公告)日：2024-02-01
申请号：US17874952
申请日：2022-07-27
IPC分类号： G06F11/14 , G06F1/24 , G06F9/4401
CPC分类号： G06F11/1417 , G06F1/24 , G06F9/4405
摘要： Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.
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公开(公告)号：US11042301B2
公开(公告)日：2021-06-22
申请号：US16219218
申请日：2018-12-13
摘要： Devices and techniques are disclosed herein for applying an effective sampling delay at a host device to one of an input signal, such as from an embedded MultiMediaCard (eMMC) device, or a clock signal. The host device can apply a configurable delay to one of the input signal or the clock signal with respect to a first edge of the clock signal, sample the input signal using the clock signal according to the configurable delay, and selectively align the sampled input signal to a subsequent, second edge of the clock signal to extend the configurable delay of the host device.
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公开(公告)号：US20180121356A1
公开(公告)日：2018-05-03
申请号：US15857435
申请日：2017-12-28
发明人： Graziano Mirichigni , Luca Porzio , Erminio Di Martino , Giacomo Bernardi , Domenico Monteleone , Stefano Zanardi , Chee Weng Tan , Sebastien LeMarie , Andre Klindworth
IPC分类号： G06F12/0804
CPC分类号： G06F12/0804 , G06F12/0891 , G06F13/00 , G06F13/1673 , G06F13/1694 , G06F2212/1024
摘要： Apparatuses and methods for providing data to a configurable storage area are described herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.
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公开(公告)号：US11309055B2
公开(公告)日：2022-04-19
申请号：US16227021
申请日：2018-12-20
发明人： Claudio Giaccio , Ferdinando Pascale , Raffaele Mastrangelo , Erminio Di Martino , Ferdinando D'Alessandro , Cristiano Castellano , Andrea Castaldo
IPC分类号： G11C29/50
摘要： Apparatus and methods are disclosed, including test systems for memory devices. Example test systems and methods include power loss logic to determine when one or more test conditions have been met in a memory operation between a host device and a memory device under test. Example test systems and methods include a function to then instruct a power management device to trigger a power loss event.
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公开(公告)号：US11282553B2
公开(公告)日：2022-03-22
申请号：US16731947
申请日：2019-12-31
发明人： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
摘要： Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US20200005840A1
公开(公告)日：2020-01-02
申请号：US16022351
申请日：2018-06-28
发明人： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
摘要： Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US20200004289A1
公开(公告)日：2020-01-02
申请号：US16022307
申请日：2018-06-28
发明人： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
IPC分类号： G06F1/12
摘要： Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US09928171B2
公开(公告)日：2018-03-27
申请号：US15637961
申请日：2017-06-29
发明人： Graziano Mirichigni , Luca Porzio , Erminio Di Martino , Giacomo Bernardi , Domenico Monteleone , Stefano Zanardi , Chee Weng Tan , Sebastien LeMarie , Andre Klindworth
IPC分类号： G06F13/00 , G06F13/16 , G06F12/08 , G06F12/0804 , G06F12/0891
CPC分类号： G06F12/0804 , G06F12/0891 , G06F13/00 , G06F13/1673 , G06F13/1694 , G06F2212/1024
摘要： Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register including a plurality of configuration bits indicative of an offset and a size, an array having a storage area, a size and offset of the storage area based, at least in part, on the plurality of configuration bits, and a buffer configured to store data, the data including data intended to be stored in the storage area. A memory control unit may be coupled to the buffer and configured to cause the buffer to store the data intended to be stored in the storage area in the storage area of the array responsive, at least in part, to a flush command.
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公开(公告)号：US20200152245A1
公开(公告)日：2020-05-14
申请号：US16731947
申请日：2019-12-31
发明人： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
摘要： Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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公开(公告)号：US10546620B2
公开(公告)日：2020-01-28
申请号：US16022351
申请日：2018-06-28
发明人： Claudio Giaccio , Ferdinando Pascale , Erminio Di Martino , Raffaele Mastrangelo , Ferdinando D'Alessandro , Andrea Castaldo , Cristiano Castellano
摘要： Devices and techniques are disclosed herein for determining, using a host device, a timing relationship between a data strobe signal, such as from an embedded MultiMediaCard (eMMC) device, and an internal clock signal. The host device can control a delay circuit using the determined timing relationship, such as to align received read data for sampling, or to determine or adjust a delay value of the delay circuit.
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