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    Time-interleaved noise-shaping successive-approximation analog-to-digital converter
    1.
    发明授权
    Time-interleaved noise-shaping successive-approximation analog-to-digital converter 有权

    公开(公告)号：US11043958B2

    公开(公告)日：2021-06-22

    申请号：US16990016

    申请日：2020-08-11

    Applicant: MEDIATEK INC.

    Inventor： Chin-Yu Lin ,  Ying-Zu Lin ,  Chih-Hou Tsai ,  Chao-Hsin Lu

    IPC: H03M1/38 ,  H03M1/08 ,  H03M1/14 ,  H03M1/12 ,  H03M1/80

    Abstract: A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.

    Charge compensation circuit and analog-to-digital converter with the same
    2.
    发明授权
    Charge compensation circuit and analog-to-digital converter with the same 有权

    公开(公告)号：US10236903B2

    公开(公告)日：2019-03-19

    申请号：US15495144

    申请日：2017-04-24

    Applicant: MEDIATEK INC.

    Inventor： Ying-Zu Lin ,  Rong-Sing Chu

    IPC: H03M1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M1/80

    Abstract: A charge compensation circuit for use in an analog-to-digital converter (ADC) includes at least one capacitor and at least one logic circuit. A first terminal of the capacitor is coupled to a reference voltage of the analog-to-digital converter. The logic circuit is configured to adjust a voltage at a second terminal of the capacitor according to a control signal. The control signal is determined according to at least one output bit from the analog-to-digital converter.

    Input buffer and analog-to-digital converter
    3.
    发明授权
    Input buffer and analog-to-digital converter 有权

    公开(公告)号：US09698813B2

    公开(公告)日：2017-07-04

    申请号：US15335193

    申请日：2016-10-26

    Applicant: MEDIATEK INC.

    Inventor： Chihhou Tsai ,  Ying-Zu Lin

    IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/1245 ,  H03M1/462

    Abstract: An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.

    Time-interleaved noise-shaping successive-approximation analog-to-digital converter
    4.
    发明授权
    Time-interleaved noise-shaping successive-approximation analog-to-digital converter 有权

    公开(公告)号：US11444634B2

    公开(公告)日：2022-09-13

    申请号：US17315571

    申请日：2021-05-10

    Applicant: MEDIATEK INC.

    Inventor： Chin-Yu Lin ,  Ying-Zu Lin ,  Chih-Hou Tsai ,  Chao-Hsin Lu

    IPC: H03M1/38 ,  H03M1/08 ,  H03M1/12 ,  H03M1/14 ,  H03M1/80

    Abstract: A time-interleaved noise-shaping successive-approximation analog-to-digital converter (TI NS-SAR ADC) is shown. A first successive-approximation channel has a first set of successive-approximation registers, and a first coarse comparator operative to coarsely adjust the first set of successive-approximation registers. A second successive-approximation channel has a second set of successive-approximation registers, and a second coarse comparator operative to coarsely adjust the second set of successive-approximation registers. A fine comparator is provided to finely adjust the first set of successive-approximation registers and the second set of successive-approximation registers alternately. A noise-shaping circuit is provided to sample residues of the first and second successive-approximation channels for the fine comparator to finely adjust the first and second sets of successive-approximation registers.

    Reference voltage generator and analog-to-digital converter
    7.
    发明授权
    Reference voltage generator and analog-to-digital converter 有权

    公开(公告)号：US09819354B2

    公开(公告)日：2017-11-14

    申请号：US15599779

    申请日：2017-05-19

    Applicant: MEDIATEK INC.

    Inventor： Chihhou Tsai ,  Ying-Zu Lin

    IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/1245 ,  H03M1/462

    Abstract: A reference voltage generator for an analog-to-digital converter (ADC) includes a current source coupled to a power supply, and a first transistor coupled between the current source and a first resistive circuit. The first resistive circuit is coupled to the first transistor. The reference voltage generator further includes a second transistor having a gate coupled to the current source and a gate of the first transistor, for providing a reference voltage to the ADC, an impedance circuit coupled to the second transistor, for selectively providing a variable impedance.

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