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公开(公告)号：US09819354B2
公开(公告)日：2017-11-14
申请号：US15599779
申请日：2017-05-19
Applicant: MEDIATEK INC.
Inventor： Chihhou Tsai , Ying-Zu Lin
CPC classification number: H03M1/1245 , H03M1/462
Abstract: A reference voltage generator for an analog-to-digital converter (ADC) includes a current source coupled to a power supply, and a first transistor coupled between the current source and a first resistive circuit. The first resistive circuit is coupled to the first transistor. The reference voltage generator further includes a second transistor having a gate coupled to the current source and a gate of the first transistor, for providing a reference voltage to the ADC, an impedance circuit coupled to the second transistor, for selectively providing a variable impedance.
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公开(公告)号：US09698813B2
公开(公告)日：2017-07-04
申请号：US15335193
申请日：2016-10-26
Applicant: MEDIATEK INC.
Inventor： Chihhou Tsai , Ying-Zu Lin
CPC classification number: H03M1/1245 , H03M1/462
Abstract: An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.
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3.发明授权公开(公告)号：US09673832B2
公开(公告)日：2017-06-06
申请号：US15134866
申请日：2016-04-21
Applicant: MediaTek Inc.
Inventor： Chihhou Tsai
CPC classification number: H03M1/08 , H03M1/0636 , H03M1/462 , H03M1/468
Abstract: A successive approximation register analog-to-digital converter (SAR ADC) with high accuracy is disclosed. Within the SAR ADC, a SAR logic circuit combines the output signal of a comparator collected during at least two successive cycles of a plurality of cycles of a search scheme of digital representation of an analog input and, accordingly, makes a one-step control for a voltage difference between a positive and a negative input terminal of the comparator. At least three capacitor network switching choices for a capacitor network of the SAR ADC are provided by the one-step control. By the one-step control, a selection between the at least three capacitor network switching choices is made according to at least two comparison results of the comparator obtained during the at least two successive cycles. In this manner, comparator noise is utilized as an additional quantization level to improve the overall ADC noise performance.
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